Digital signal isolation

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus expansion or extension

Reexamination Certificate

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Details

C327S379000, C327S488000

Reexamination Certificate

active

06704826

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to isolation of digital signals. More particularly, the invention relates to the use of CMOS logic gates to isolate two or more digital circuits from each other. The invention also relates to isolating “hot plug” digital circuits.
2. Background of the Invention
In digital electronic systems, such as computer systems, that have power conservation capability, power is sometimes turned off to part of the system that is not being used, while other parts of the system remain on and functional. Laptop computers, for example, can transition automatically to a power state in which the display and hard drive are turned off to conserve power if the computer has been inactive for a predetermined period of time (e.g., 5 minutes). Many desktop systems also have this capability.
It is commonly assumed that digital signals provided by the un-powered circuit in the computer system are at a logic zero state. However, if the un-powered circuit does not share a common electrical ground with the powered circuit, the output signal lines from the un-powered circuit could float relative to the ground voltage of the powered circuit. These floating signals can cause undesirable effects on the system. For instance, current may flow on the floating signal lines from the un-powered circuit, thereby hastening the drain on the battery in a battery powered laptop computer. Further, undesirable signal oscillations can result from the floating signals. Accordingly, there is a need to solve these problems.
BRIEF SUMMARY OF THE INVENTION
The problems noted above are solved in large part by a digital isolation circuit that comprises a plurality of CMOS transistors. The transistors may be connected together to form either a logic NAND gate or a logic NOR gate, but the isolation circuits preferably are not used to provide the NAND or NOR logic functions. The isolation circuit isolates one input data signal from an output signal in response to a control input signal. If the control signal is driven to one state (e.g., logic
1
), the isolation circuit can be made to function as an inverter when no isolation is needed. In the opposite logic state, the control signal causes the isolation circuit to isolate the input data signal from the output signal. The digital isolation circuit solves the problems noted above.


REFERENCES:
patent: 6169801 (2001-01-01), Levasseur et al.
patent: 6434633 (2002-08-01), Braun et al.

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