Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2003-12-22
2008-05-06
Lamarre, Guy J. (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S794000, C714S795000, C714S792000, C375S262000, C375S341000, C375S265000
Reexamination Certificate
active
07370266
ABSTRACT:
A digital signal decoding device according to an aspect of the present invention is a digital signal decoding device for generating a binary code sequence by maximum likelihood estimation from a convolutionally encoded input signal sequence, includes an add-compare-select unit configured to compare only two metric values one unit time before the calculation time of a predetermined branch metric value calculated from the input signal sequence at two successive times at each time, to add the predetermined branch metric value to the two metric values independently of the compare process, to select one of the two sums in accordance with the comparison result of the two metric values, and to output the selected value as a metric value to be used at the next time.
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Inkyu Lee et al., “A New Architecture For The Fast Viterbi Algorithm,” Global Telecommunications Conference 2000 GLOBECOM '00, vol. 3, 2000, pp. 1664-1668.
Kabushiki Kaisha Toshiba
Lamarre Guy J.
Pillsbury Winthrop Shaw & Pittman LLP
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