Digital signal clock recovery

Details Digital signal clock recovery Digital signal clock recovery

1996-08-01

1999-08-24

Bocure, Tesfaldet

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375360, H04L 700

Patent

active

059433787

ABSTRACT:
A clock recovery circuit for recovering a symbol clock (226) includes a level decoder (210) for determining one of a plurality of received states of a demodulated signal (105) during each symbol period of the symbol clock (226). Each of the plurality of received states corresponds to one of at least two modulation levels. The level decoder (210) generates for each of the plurality of received states a sign signal (212) having transitions at central threshold transition times and a magnitude signal (211). An edge selector (220) determines selected central threshold transition times. A synchronizable clock (225) is synchronized by the selected central threshold transition times, resulting in a significant reduction of symbol clock (226) jitter.

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patent: 5528634 (1996-06-01), Criph et al.
patent: 5654987 (1997-08-01), Nakamura

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