Digital signal buffer circuit

Details Digital signal buffer circuit Digital signal buffer circuit

2006-12-12

2006-12-12

Cho, James (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S027000, C327S274000

Reexamination Certificate

active

07148726

ABSTRACT:
A delay circuit is provided with a plurality of variously sized equalization transistors, a plurality of equalization resistors having different resistance values, a plurality of equalization capacitors having difference capacitance values, and switch circuits. The switch circuits are used to make selections from among the equalization transistors, equalization resistors, and equalization capacitors for the purpose of adjusting the amplitude level and delay amount of a digital inverse signal.

REFERENCES:
patent: 6351191 (2002-02-01), Nair et al.
patent: 6498511 (2002-12-01), Tamura et al.
patent: 6831492 (2004-12-01), Abbasi et al.
patent: 6956442 (2005-10-01), Groen et al.
patent: 6975132 (2005-12-01), Groen et al.
patent: 2003-204291 (2003-07-01), None
Sherif Galal, et al. “10Gb/s limiting Amplifier and Laser/Modulator Driver in 0.18 μm CMOS Technology”, ISSCC 2003, Digest of Technical Papers, pp. 188-189, no month.

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