Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2001-04-09
2004-01-20
Kim, Hong (Department: 2186)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C710S308000, C711S163000, C711S203000
Reexamination Certificate
active
06681346
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is directed to digital processing systems, in general, and more particular to a digital processing system including a DMA controller operating in the virtual address domain and a method of operating the same.
In conventional digital processing systems, a direct memory access (DMA) controller is used to transfer digital words from one location in physical memory to another. Typically, DMA controllers operate with physical memory addresses. The DMA controller generally has registers that may be programmed by a central processing unit (CPU) of the system under control of a user program, for example, with source addresses, destination addresses, number of words to be transferred during an access task, the type of the task, be it a memory to memory operation, for example, and control bits that permit the DMA controller to carry out the transfer autonomously without substantial intervention from the CPU. Ideally, the CPU can off-load the processing burden of a transfer of a block of digital words between memory locations so that it may perform other tasks in parallel with the DMA controller.
In processing systems which operate in both a virtual address domain and a physical address domain, a memory management unit (MMU) is used to translate between virtual addresses and physical memory addresses. The MMU is also used to protect memory from being improperly written into or read from, and to detect faulty memory. But, the MMU primarily coordinates its functions with the CPU and is not conventionally used with the DMA controller. Accordingly, if the DMA controller is directed to write digital words into a proper location in memory, but for some reason, it incurs a fault or upset in its address register, it could write into an improper location, like portions of the operating system, for example. Since there is no feedback to the MMU or CPU, this condition could remain dormant until the affected code is executed which could lead to devastating consequences to the system. The same could be said for improper read access tasks as a result of faults or upsets in the address register of the DMA controller. The system has no way currently of identifying such a fault in the DMA controller.
The MMU with appropriate error detection and correction (EDAC) capabilities does detect faults in the memory of the system, such as a bad bank of registers, for example, and may bring them to the attention of the CPU. However, in order to compensate for the faulty memory, the user or application software which directs DMA transfers would have to be reprogrammed to change the originally programmed physical source and/or destination addresses to new physical addresses which are not part of the faulty memory. This reprogramming, while possible, will involve modification of at least as many application software routines as can directly program the DMA system. The reprogramming of these routines will cost execution time and will have a detrimental affect on real-time embedded systems.
Another area of concern is the security of conventional processing systems. For example, errant software programs which direct DMA transfers could improperly use the DMA controller and cause problems in the system operation. This is a condition for which additional security protection is needed.
The present invention overcomes the aforementioned drawbacks of the conventional processing systems and offers security protection not currently present in these conventional systems.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a digital processing system comprises a central processing unit (CPU) operating in a virtual address domain for executing both operating system software and user software to perform various processing tasks; a direct memory access (DMA) controller; a memory management unit (MMU) programmed to translate virtual memory addresses to physical memory addresses; and a plurality of memory blocks for storing digital words in registers having physical addresses; wherein the DMA controller is governed by the CPU and is operable in the virtual address domain for controlling a transfer of digital words from a source block of memory to a destination block of memory through the MMU which translates the virtual source and destination memory addresses received from the DMA controller to corresponding source and destination physical addresses of the memory.
In accordance with another aspect of the present invention, a method of operating a digital processing system comprises the steps of: storing digital words in registers having physical addresses of a plurality of memory blocks; programming a memory management unit (MMU) to translate virtual memory addresses to physical memory addresses; governing a direct memory access (DMA) controller to operate in the virtual address domain for controlling a transfer of digital words from a source block of memory to a destination block of memory through the MMU; and translating the virtual source and destination memory addresses received from the DMA controller in the MMU to corresponding source and destination physical addresses of the memory.
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James Robert Ward
Waldie Arthur Howard
Calfee Halter and Griswold LLP
Goodrich Corporation
Kim Hong
Percio David R.
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