Digital processing apparatus using two synchronization signals

Details Digital processing apparatus using two synchronization signals Digital processing apparatus using two synchronization signals

1995-09-27

1997-09-23

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

348500, 386 91, H04L 700, H04L 504, H04L 944

Patent

active

056712600

ABSTRACT:
The digital processing apparatus includes a high speed response PLL that produces a first clock signal locked on the horizontal synchronization signal included in the video signal input thereto. An analog to digital converter converts the input video signal with respect to the first clock signal into a digitized video signal. A write controller controls a video memory to store the digitized video signal based on the first clock signal. A low speed response PLL produces a second clock signal based on the vertical synchronization signal included in the video signal. A read controller controls the video memory to read out the stored digitized video signal therefrom based on the second control signal. The digital processing apparatus can store and read the digitized video signal to and from the video memory stably, enabling the video signal read from the video memory to be processed effectively and securely.

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patent: 4791498 (1988-12-01), Yoshihiro
patent: 4853781 (1989-08-01), Okano et al.
patent: 5065230 (1991-11-01), Kumano et al.
patent: 5204787 (1993-04-01), Suzuki et al.
patent: 5245430 (1993-09-01), Nishimura

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