Digital PLL (phase-locked loop) frequency synthesizer

Details Digital PLL (phase-locked loop) frequency synthesizer Digital PLL (phase-locked loop) frequency synthesizer

2001-03-05

2002-03-19

Ghebretinsae, Temesghen (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S156000, C327S158000, C331SDIG002

Reexamination Certificate

active

06359950

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a digital PLL (Phase-Locked Loop) frequency synthesizer, in which a reference frequency formed by the division of a stable quartz oscillator frequency is compared with a second frequency, derived by dividing the frequency of a voltage-controlled oscillator, in a phase-frequency detector whose output signal serves, after being led via an optionally provided charge pump and a loop low-pass filter in the PLL loop, as control voltage for the voltage-controlled oscillator. For the purpose of dividing the frequency of the voltage-controlled oscillator there is provided in the PLL loop an N/(N+1) frequency divider, which can be switched over between two adjacent integral divisor factors N and N+1, divides by N for the duration of M-K cycles, and then divides by N+1 for the duration of K cycles. For the purpose of causing automatic switching over of the N/(N+1) frequency divider there is provided a phase accumulator to whose contents the value K with a modulo-M addition is added with each pulse of the divided VCO frequency and which causes a change in the divisor factor from N to N+1 in the next cycle after each overflow.
Conventional digital PLL frequency synthesizers operate using the known principle illustrated in the form of a block diagram in FIG.
1
. There, a reference frequency f
Ref
, which is formed by downward division of a stable quartz frequency f
Q
generated with the aid of a crystal-controlled oscillator
1
, by the divisor factor ‘R’ with the aid of a reference frequency divider
2
, is compared in a phase-frequency detector
3
with a second frequency f
2
which is derived by dividing a frequency f
VCO
generated in a voltage-controlled oscillator (VCO)
4
by the divisor factor N. This frequency division by the divisor factor ‘N’ is performed in an N-frequency divider
5
. The phase-frequency detector
3
generates—depending on the design together with a charge pump
6
—and a loop low pass filter
7
, the control voltage which causes the voltage-controlled oscillator
4
to oscillate at a desired frequency f
VCO
.
The divider ratio ‘N’, which can be set by the N-frequency divider
5
, is integral, which means that the voltage-controlled oscillator
4
can oscillate only at an integral multiple of the reference frequency f
Ref
when the phase-locked loop is locked. This fact is attended by some disadvantages.
A low reference frequency f
Ref
must be used for a desired small spacing between the frequencies f
VCO
which can be generated in the voltage-controlled oscillator
4
. Since the phase-locked loop PLL constitutes a sampled system with the sampling frequency f
Ref
, the sampling theorem (Nyquist theorem) can be used to obtain a stable system by selecting the bandwidth of the phase-locked loop PLL to be not higher than f
Ref
/2. In practice, the bandwidth is usually at approximately 10% of the reference frequency f
Ref
.
However, a small PLL bandwidth means a slow transient response upon switching over the N-frequency divider
5
in order to set another frequency f
VCO
of the voltage-controlled oscillator
4
, that is to say another frequency channel.
Another disadvantage stems from the fact that the frequency f
VCO
of the voltage-controlled oscillator
4
must be divided very far downward. Since the divided frequency f
VCO
is compared with the reference frequency f
Ref
, which must have low phase noise, although the phase noise of the divided frequency f
VCO
is optimized by the PLL control, the phase noise of the voltage-controlled oscillator
4
itself is worsened as the divisor factor ‘N’ increases.
A reference frequency f
Ref
which is higher than the required channel allocation, can be used whenever the divisor factor ‘N’ can no longer be set integrally. Since the N-frequency divider
5
itself can divide only by integral factors, the fractional divider ratio must be set as the time average over M cycles, that is to say it is necessary to divide by the divisor factor ‘N’ for the duration of M-K cycles, and then to divide by the divisor factor ‘N+1’ increased by the whole number ‘1’ for the duration of K cycles.
The result of this in the case of a steady-state phase-locked loop PLL is a mean frequency f
VCO
of the voltage-controlled oscillator
4
of:
f
VCO
=f
Ref
*(N+K/M).
Starting from a stable frequency f
VCO
, set in accordance with the desired fractional divider ratio, of the voltage-controlled oscillator
4
, it can be shown that the frequency f
VCO
/N is too high during the cycles in which division is by the divisor factor ‘N’, and that therefore the phase difference between the reference frequency f
Ref
and the frequency f
VCO
/N is increased by the factor
T
VCO-setpoint
*K/M
at each pass.
This accumulated phase difference grows to a maximum of one VCO period of the voltage-controlled oscillator
4
, and is raised again overall precisely in those cycles in which division is by the divisor factor ‘N+1’, with the result that after M periods of the reference frequency f
Ref
phase coincidence prevails again between the reference frequency f
Ref
and the divided frequency f
VCO
. The factor M is the modulus, that is to say the greater the factor M, the higher it is possible to select the reference frequency f
Ref
, and the smaller the frequency steps, that is to say the smaller the frequency channel spacings can be set.
Circuit proposals are known which permit a phase accumulator to be used to switch over the divisor factor of the N/(N+1) divider automatically. The value K with a modulo-M addition can be added again to the contents in a phase accumulator after each pulse of the divided frequency f
VCO
from the voltage-controlled oscillator. After each overflow of the phase accumulator, the divisor factor of ‘N’ is changed to ‘N+1’ in the next cycle. It is implicit therefrom that the phase accumulator always has a value which, when multiplied by the factor T
VCO-setpoint
/M represents the current phase value at the phase-frequency detector.
Because of the phase difference which is set up at the phase-frequency detector in each cycle, the PLL will, however, attempt to keep correcting the voltage-controlled oscillator (VCO), and will therefore have a negative influence on the phase stability. Consequently, a constant VCO frequency and VCO phase require a constant control voltage at the voltage-controlled oscillator, and thus a large time constant of the loop low pass filter, and this precisely contradicts the desire for a larger loop bandwidth.
Various approaches to a solution have become known for the purpose of achieving a reduction in phase jitter. One such prior art method (from the Marconi company) consists in using a plurality of cascaded phase accumulators which use the sigma-delta principle to drift the frequency components of the phase jitter into regions which are strongly damped by the loop low pass filter. No compensation is then required anymore. However, a plurality of phase accumulators are required.
Another prior art method for reducing phase jitter is active compensation of control by interventions at the phase-frequency detector or at the loop low pass filter. In this case, for example, it is possible in addition to the actual charge pump current to feed a compensation current into the loop low pass filter in order to compensate the effect of the first-named current. In this case, it is necessary to vary either the magnitude or the duration of the feed from cycle to cycle, in order to make available for compensation purposes a charge quantity dependent on the phase error.
The individual graduations of the different charge quantities depend on the desired frequency f
VCO
of the voltage-controlled oscillator and can, for example, be set as a function of a reference current which depends on the VCO frequency/period. The current compensation principle is used in the case, for example, of the so-called fractional-N phase locked loops (PLLs) built by the Philips company. The disadvantage of this method r

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