Digital PLL device

Details Digital PLL device Digital PLL device

2008-03-11

2008-03-11

Payne, David C. (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C329S307000, C329S360000, C332S127000, C342S103000, C375S215000, C375S294000, C375S327000, C388S911000, C455S067160, C455S260000, C455S276100, C455S180300

Reexamination Certificate

active

07342986

ABSTRACT:
A phase-locked-loop device includes a clock generator for generating a reference clock based on a binarized playback signal and a frequency of run-length data and for generating N-phase clocks using the reference clock, a pulse-length measuring device for measuring a pulse length of the binarized playback signal using the N-phase clocks to output pulse-length data, and a run-length-data extracting device for counting the pulse-length data based on a virtual channel clock to extract run-length data. Pulse-length data is generated using the N-phase clocks (e.g., 16-phase clocks). The pulse-length data is counted based on the virtual channel clock to extract run-length data. Thus, it is not needed to generate a high-frequency clock, and the operating frequency is maintained sufficiently low.

REFERENCES:
patent: 5005164 (1991-04-01), Sakamoto et al.
patent: 6424192 (2002-07-01), Lee et al.
patent: 2003/0103591 (2003-06-01), Noguchi
patent: 09-247137 (1997-09-01), None
patent: 11-341306 (1999-12-01), None

Affiliated with

Also associated with

Rating

Digital PLL device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital PLL device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital PLL device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2808096