Digital PLL circuit with low power consumption

Details Digital PLL circuit with low power consumption Digital PLL circuit with low power consumption

1993-02-18

1995-09-19

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375354, 375571, 331 25, H03D 324

Patent

active

054523265

ABSTRACT:
The present invention is directed to a digital PLL (phase locked loop) circuit. A phase of an output clock is advanced by about 360.degree. at every master clock. Only when there is a data edge having a large input level, a phase difference is calculated and the output clock frequency becomes a frequency deviated amount. Therefore, an electric power consumption can be reduced and an AGC (automatic gain control) function is presented in the input data. Further, the digital PLL circuit can be given free running control and leakage secondary PLL characteristics so that the digital PLL circuit can be enhanced in efficiency. Therefore, there is provided the clock reproducing digital PLL circuit of high efficiency which can reduce an electric power consumption.

REFERENCES:
patent: 3778723 (1973-12-01), Schaefer
patent: 4052558 (1977-10-01), Patterson
patent: 4577163 (1986-03-01), Culp
patent: 4791378 (1988-12-01), Waltham
patent: 4855683 (1989-08-01), Troudet et al.
patent: 5036294 (1991-07-01), McCaslin
patent: 5182761 (1993-01-01), Beyer et al.
patent: 5272730 (1993-12-01), Clark

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