Digital PLL circuit having signal edge position measurement

Details Digital PLL circuit having signal edge position measurement Digital PLL circuit having signal edge position measurement

1993-09-10

1995-06-27

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375373, H04L 700

Patent

active

054286484

ABSTRACT:
A ring oscillator has its inverter states in respective inner stages change at a time unit longer than a period of a master clock MCK and is oscillated at a period longer than the period of the master clock MCK. The inverter states of the respective stages of the ring oscillator are captured by a flipflop circuit and a value indicating each of these states is subtracted by a subtractor from numerical figures indicating the inverter states in the respective stages of the ring oscillator as captured at the timing of the master clock MCK by other flipflop circuits. The difference is output as a signal indicating the position of the input signal edge.

REFERENCES:
patent: 3878473 (1975-04-01), Furtney, Jr.
patent: 4456890 (1984-06-01), Carickhoff
patent: 4841551 (1989-06-01), Avaneas
patent: 4954824 (1990-09-01), Yamada et al.
patent: 5023892 (1991-06-01), Stoica
patent: 5077529 (1991-12-01), Ghoshal et al.
patent: 5166959 (1992-11-01), Chu et al.
Patent Abstracts of Japan, vol. 13, No. 128 corres. to JP-1,019,826 (Fukuda).
Patent Abstracts of Japan, vol. 13, No. 123, corres. to JP-63-292,825 (Fukuda).
The article appearing in Electronic Components and Applications, vol. 9, No. 2, 1989 (Rosink).
The article appearing in International Symposium on Circuits and Systems, vol. 4, May 1990 (Kajiwara et al.).

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