Digital PLL circuit and signal regeneration method

Details Digital PLL circuit and signal regeneration method Digital PLL circuit and signal regeneration method

1998-12-04

2003-04-29

Chin, Stephen (Department: 2734)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C370S518000, C327S150000, C327S152000, C327S153000, C327S159000, C327S161000

Reexamination Certificate

active

06556640

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a digital PLL (Phase Locked Loop) circuit and a signal regeneration method, and in particular, to a digital PLL circuit and a signal regeneration method which are employed in optical communication systems such as PON (Passive Optical Network) including PDS (Passive Double Star) etc.
DESCRIPTION OF THE PRIOR ART
These days, high speed and high volume data transmission is being more and more required due to development and enlargement of telecommunication techniques. In order to meet such requirements, considerable studies have been done on digital PLL circuits for quickly extracting a clock signal from burst input data signal and executing quick signal regeneration from the burst input data signal, and on signal regeneration methods utilizing such digital PLL circuits, as disclosed in Proceedings of the 1997 Electronics Society Conference of ICICE (the Institute of Electronics, Information and Communication Engineers (Japan)), C-12-25, C-12-26, Proceedings of the 1996 Electronics Society Conference of ICICE, SC-13-5, Proceedings of the 1996 Communications Society Conference of ICICE, B-844, etc.
In general, in order to realize such a high speed digital PLL circuit, digital PLL circuits are required “quick extraction”, that is, the capability of extracting and outputting an extracted clock signal and a regenerated data signal from burst input data signal at high speed (within a few bits).
Here, the “extraction” means an operation of the digital PLL circuit for extracting a regenerated data signal having no errors from the burst data signal which is inputted to the digital PLL circuit.
And a word “extraction time” is used in the sense that will be described below.
FIGS. 1A and 1B
are schematic diagrams for explaining the meaning of the word “extraction time”.
FIG. 1A
shows an input data signal which is supplied from a terminal to the digital PLL circuit, and
FIG. 1B
shows a regenerated data signal which has been regenerated by the digital PLL circuit from the input data signal. Referring to
FIG. 1A
, the input data signal includes an overhead and a data area. The overhead is provided as the preamble of the data signal and is used as training bits for the digital PLL circuit. In
FIG. 1A
, each bit in the data area of the input data signal is assigned a bit number, in which the assignment is started at the front end of the data area. In
FIG. 1B
, each bit in the data area of the regenerated data signal is also assigned a bit number in the same way. Referring to the regenerated data signal of
FIG. 1B
, part in the data area starting from the third bit could be regenerated by the digital PLL circuit without errors. Therefore, the “extraction time” in the case of
FIGS. 1A and 1B
is 3 bits. In the following, the important concept “extraction time” will be used in the sense that has been explained above.
In the following, a conventional digital PLL circuit and its signal regeneration method will be explained referring to FIG.
2
.
FIG. 2
is a schematic block diagram showing a conventional digital PLL circuit which has been proposed by the present inventor.
The digital PLL circuit shown in
FIG. 2
comprises a data sampling section
1
, a data regeneration section
3
, an edge point detection operation section
4
, and a clock signal extraction section
5
.
The data sampling section
1
is supplied with an input data signal
10
and an N-phase clock signal
11
(N: integer larger than 1) which is composed of N clock signals whose frequencies are almost the same as the bit rate of the input data signal
10
and whose phases has been successively shifted by 1/N of the clock cycle. The data sampling section
1
digitally samples the input data signal
10
using the N-phase clock signal
11
, and thereby outputs a parallel sample data signal
6
which is composed of N sample data signals.
The edge point detection operation section
4
is supplied with the parallel sample data signal
6
outputted by the data sampling section
1
and an extracted clock signal
12
which is outputted by the clock signal extraction section
5
. The edge point detection operation section
4
acquires the N sample data signals of the parallel sample data signal
6
with timing in sync with the extracted clock signal
12
, obtains a clock phase number which indicates the position of a rising edge in the input data signal
10
in one cycle of the extracted clock signal
12
and a clock phase number which indicates the position of a falling edge in the input data signal
10
in one cycle of the extracted clock signal
12
, calculates the average of the clock phase numbers concerning the rising edges in a predetermined period till the moment and the average of the clock phase numbers concerning the falling edges in a predetermined period till the moment, obtains the number of rising edges and the number of falling edges of the input data signal
10
in one cycle of the extracted clock signal
12
, and outputs an edge point operation output signal
8
which includes information on the average clock phase number concerning the rising edges, information on the average clock phase number concerning the falling edges, and information on the number of rising edges and the number of falling edges of the input data signal
10
in one cycle of the extracted clock signal
12
.
The clock signal extraction section
5
is supplied with the N-phase clock signal
11
and the edge point operation output signal
8
outputted by the edge point detection operation section
4
. The clock signal extraction section
5
selects a clock signal from the N clock signals composing the N-phase clock signal
11
based on the information of the edge point operation output signal
8
, and outputs the selected clock signal as the extracted clock signal
12
.
The data regeneration section
3
is supplied with the parallel sample data signal
6
outputted by the data sampling section
1
, the edge point operation output signal
8
outputted by the edge point detection operation section
4
, and the extracted clock signal
12
outputted by the clock signal extraction section
5
. The data regeneration section
3
selects one sample data signal from the N sample data signals of the parallel sample data signal
6
based on the information of the edge point operation output signal
8
, and outputs the selected sample data signal as a regenerated data signal
13
in sync with the extracted clock signal
12
.
In the digital PLL circuit shown in FIG.
2
and its signal regeneration method, the parallel sample data signal
6
including the N sample data signals is obtained by the data sampling section
1
, by digitally sampling the input data signal
10
using the N-phase clock signal
11
which is composed of N clock signals whose frequencies are almost the same as the bit rate of the input data signal
10
and whose phases has been successively shifted by 1/N of the clock cycle. Edge points of the input data signal
10
in one cycle of the extracted clock signal
12
are detected by referring to the N sample data signals of the parallel sample data signal
6
and the edge point operation output signal
8
including the information on the edge points are generated, by the edge point detection operation section
4
, The extracted clock signal
12
is selected by the clock signal extraction section
5
from the N clock signals of the N-phase clock signal
11
based on the information of the edge point operation output signal
8
. And one sample data signal is selected by the clock signal extraction section
5
from the N sample data signals of the parallel sample data signal
6
based on the information of the edge point operation output signal
8
and the selected sample data signal is outputted as a regenerated data signal
13
in sync with the extracted clock signal
12
.
Such digital PLL circuits and signal regeneration methods are generally utilized for realizing bi-directional optical communication via optical fiber in optical communication systems such as PDS (Passive Double St

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