Digital PLL circuit and clock generation method

Details Digital PLL circuit and clock generation method Digital PLL circuit and clock generation method

1999-02-10

2001-08-14

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S376000, C327S147000, C327S151000, C327S152000, C331S002000, C331S060000

Reexamination Certificate

active

06275553

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a digital PLL circuit and a clock generation method, and more particularly to a digital PLL circuit that provides immunity with respect to, for example, externally introduced noise or power supply noise, and which also enables the output of a stable clock with a constant phase.
BACKGROUND OF THE INVENTION
In a display apparatus that is connected to a computer, display is performed in synchronization with external vertical and horizontal synchronization signals. In particular, a clock of high accuracy is required to control the horizontal scanning lines based on the horizontal synchronization signal, and unless a jitter-free clock is provided, the display will be distorted or will undulate.
A circuit of the past is shown in
FIG. 9
, this circuit being formed by a crystal oscillator circuit
61
, a frequency detection circuit
60
, a phase comparator circuit
62
, a filter
63
, a VCO (voltage controlled oscillator)
64
, and a 1/M frequency divider circuit
69
.
The frequency detection circuit
60
counts the period of the horizontal synchronization signal
102
with the clock of the crystal oscillator circuit
61
that oscillates at a known frequency, and sets the divisor of the 1/M frequency divider circuit
69
.
The phase of the output
205
of the 1/M frequency divider circuit
69
is compared to the phase of the horizontal synchronization signal
102
by the phase comparator circuit
62
, the results thereof being smoothed by the filter
63
, and used to control the VCO
64
.
In this circuit, which is known as a phase-locked loop circuit, because a voltage that is smoothed by the filter
63
establishes the oscillation frequency of the VCO
64
, if external noise or power supply noise is allowed to be superimposed, a variation will occur in the oscillation frequency of the VCO
64
, thereby causing jitter in the system clock
204
.
Additionally, regarding the frequency of the system clock
204
that is required with respect to the frequency of the horizontal synchronization signal
102
that is input, the divisor M of 1/M frequency divider circuit
69
is several thousand, so that the phase comparison is only performed for one clock out of several thousand clocks, the result being that it is difficult to apply feedback of the phase comparison results, thereby requiring time for the frequency to settle back to the original frequency when it is caused by change by external noise, this manifesting itself as noise-caused jitter.
A known technology for lessening the above-noted jitter is disclosed in the Japanese Unexamined Patent Publication (KOKAI) H2-14618.
Accordingly, it is an object of the present invention to provide a novel PLL circuit and clock generation method that improves on the above-noted problems, which particularly provides immunity with respect to external noise and power supply noise, and also enables the output of a stable clock with a constant phase.
SUMMARY OF THE INVENTION
In order to achieve the above-noted objects, the present invention adopts the following basic constitution.
Specifically, a first aspect of a digital PLL circuit according to the present invention has a first PLL circuit comprising a reference oscillator, a voltage-controlled oscillator and a 1/N frequency divider which divisor is unvaried, said 1/N frequency divider dividing the oscillation output of said voltage-controlled oscillator by means of said 1/N frequency divider, comparing the phases of an output signal of said 1/N frequency divider and an output signal of said reference oscillator, controlling the oscillation frequency of said voltage-controlled oscillator, and extracting an oscillation output of said voltage-controlled oscillator; a signal generation circuit generating a plurality of output signals having the same frequency as a frequency from said voltage-controlled oscillator of said first digital PLL circuit but differing phase; a second digital PLL circuit comprising a signal selecting circuit that is capable of selecting a signal from said signal generation circuit, a variable frequency divider circuit that divides the frequency of an output of said signal selecting circuit, a phase comparator circuit that compares the phases of a reference signal and the output signal from said variable frequency divider circuit, an up/down counter that detects a difference in phase of said phase comparator circuit, a digital filter that is provided between said up/down counter and said signal selecting circuit, this second PLL circuit selecting the signal from said signal generation circuit based on the output of said up/down counter, a clock that is synchronized with the phase of said reference signal being obtained by said second PLL circuit, and said clock being phase-compared N times by said first digital PLL circuit in a time between two of said reference signal.
In a second aspect of the digital PLL circuit according to the present invention, said voltage-controlled oscillator of said first digital PLL circuit is formed by a loop connection of an odd number of inverter circuits in cascade, and said first digital PLL circuit forming so as to following relationship between the allowable jitter time of said clock, oscillation period of said reference oscillator, the divisor of the 1/N frequency divider circuit, and the number of inverter circuit stages of said voltage-controlled oscillator(VCO).
Allowable clock jitter time
>(Reference oscillator period)/{( Divisor of 1/N frequency divider)×(Number of inverter circuit stages in VCO)×2}
In a third aspect of the digital PLL circuit according to the present invention, said signal generation circuit is configured so as to extract several signals having differing phases from connection lines between said inverter circuits, and said signals of differing phase by 180 degrees are extracted from said connection lines.
In a fourth aspect of the digital PLL circuit according to the present invention, said signal selecting circuit is provided with a switching means for the purpose of selecting one signal from a plurality of signals having differing phases, said signals being output from said signal generation circuit.
In a fifth aspect of the digital PLL circuit according to the present invention, said reference signal in said second digital PLL circuit is a horizontal synchronization signal.
One aspect of a method of generating a clock in a digital PLL circuit according to the present invention is that a plurality of signals having differing phases are generated from a first digital PLL circuit which is provided with unvaried frequency divider, a prescribed signal being selected from said plurality of signals, said selected signal being divided by variable frequency divider of a second digital PLL circuit, the phase of said divided signal being compared by a phase comparator circuit of a second digital PLL circuit with the phase of a reference signal and, based on a result of said comparison, a signal being selected from said plurality of signals so as to eliminate said phase difference between said divided signal and said reference signal, thereby obtaining a clock that is synchronized to the phase of said reference signal.
This PLL circuit is formed by a first PLL circuit and a second PLL circuit, the voltage-controlled oscillator of the first PLL circuit generating output signals having the same frequency but each phase is different, the second PLL circuit selecting one of the plural output signals of the first PLL circuit so as to eliminate the phase difference between the reference signal and the output signal of the first PLL circuit that are input to the second PLL circuit phase comparator.
That is, the present invention has a crystal oscillator circuit as the reference clock, the oscillation clock
101
thereof being multiplied by the first digital PLL circuit
51
, and the resulting output reference clock
103
therefrom being switched by the signal switching circuit
8
of the second digital PLL circuit
52
so as to obtain a system clock
104
that

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