Digital PLL circuit and actuating method

Details Digital PLL circuit and actuating method Digital PLL circuit and actuating method

1997-05-01

1999-03-16

Chan, Jason

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

327156, H03D 324

Patent

active

058839305

ABSTRACT:
In a DPLL circuit used in a receiver for radio data communication employing the GMSK modulation system, a data latch circuit 23 and subtractor 24 find the phase information difference for each symbol from the incoming phase data. A modulation component removal circuit 25 removes the modulation component from the phase information difference. A frequency error calculating circuit 26 integrates the phase information difference over an interval of n symbols, multiplies this integrated value by 1
, and takes the result as the mean frequency error value for the interval of n symbols, and then outputs this to loop filter 32. A phase error calculating circuit 27 further integrates over an interval of n symbols the integrated value from the frequency error calculating circuit, and multiplies the result by 2
. Adder 28 adds an initial phase latched by a data latch circuit 22 to the output of the phase error calculating circuit, and outputs the result to NCO 33 as the phase error value. Operation of loop unit 36 is commenced with a timing that is preset by the mean frequency error value and phase error value.

REFERENCES:
patent: 4375694 (1983-03-01), Kuhn
patent: 4423390 (1983-12-01), Waters
patent: 4780844 (1988-10-01), Keller
patent: 5381116 (1995-01-01), Nuckolls et al.
patent: 5539357 (1996-07-01), Rumreich
patent: 5572157 (1996-11-01), Takashi et al.
patent: 5572558 (1996-11-01), Beherns
patent: 5598448 (1997-01-01), Girardeau, Jr.
M. Hata, "Examples of design of PLL control circuits", Dec. 18, 1987, p. 38 .

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