Digital PLL circuit

Details Digital PLL circuit Digital PLL circuit

1998-05-22

2001-05-22

Pham, Chi (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S371000, C375S362000, C375S375000

Reexamination Certificate

active

06236696

ABSTRACT:

BACKGROUND OP THE INVENTION
1. Field of the Invention
The present invention relates to a digital PLL (phase-locked loop) circuit, and more particularly to a digital PLL circuit suitable for a receiver which receives a data signal in bursts including duty fluctuations and jitters.
2. Description of the Related Art
A typical PLL circuit uses a low-pass filter (LPF) to remove high frequency components from an error signal generated by a phase comparator. The oscillation frequency of a VCO (voltage-controlled oscillator) is controlled with the smoothed error signal to tune its output frequency to the input data. In the case where such a PLL circuit is applied to a burst-like digital data signal varying in phase due to frequency deviation, duty fluctuation, a jitter and so forth, the PLL circuit needs a long phase tuning time and further brings about errors when retiming the received data on the basis of a separate clock.
To solve the above problem, Baba, one of the present inventors, Invented a new digital PLL circuit and made a Japanese patent application on Mar. 1. 1995 (Japanese Patent Application No. 7-41132). The United States Patent was obtained for the same (U.S. Pat. No. 5,687,203). The digital PLL circuit is provided with a data sampling circuit which samples input data in response to N phase clocks in the direction of (received) time. The phase of the clock corresponding to, among the sampled data, the data in which edges are evenly
detected is used as a first phase or reference clock. The N phase sampled data signals are rearranged in synchronism with the first phase clock to thereby generate N phase rearranged data signals from which an optimal sampled data signal is selected. The digital PLL circuit can cope with frequency deviation, duty fluctuation, a jitter and so forth.
However, in the case of fluctuation or deviation of 50% or more, there may be cases where an identification point at which the input data is identified is erroneously determined, leading to an error when retiming the input data.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above problems, and therefore an object of the present Invention is to provide a digital PLL circuit which can rapidly extract a timing clock from a burst-like digital data signal varying in phase due to frequency deviation, duty fluctuation, a jitter and so forth so as to identify the input data signal without any error.
In order to achieve the above object, according to the present invention, a digital PLL circuit is provided with a sampler for sampling a burst data signal depending on N phase clock signals to produce N phase sampled data signals. Based on the N phase sampled data signals, an edge phase detector detects edge information in synchronization with a reference signal. The digital PLL circuit is further provided with a duty detector for detecting duty information based on the N phase sampled data signals in synchronization with the reference signal. A selector selects an optimal sampled data signal from the N phase sampled data signals depending on the edge information and the duty information, and a retiming section retimes the sampled data signal selected in synchronization with the reference signal.
The above and other objects and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5414736 (1995-05-01), Hasegawa et al.
patent: 5552727 (1996-09-01), Nakao
patent: 5553104 (1996-09-01), Takashi et al.
patent: 5557648 (1996-09-01), Ishihara
patent: 5867541 (1999-02-01), Tanaka et al.
patent: 6025743 (2000-02-01), Abe
patent: 6034998 (2000-03-01), Takashi et al.
patent: 7-41132 (1995-01-01), None
patent: 8-237117 (1996-09-01), None

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