Digital PLL circuit

Details Digital PLL circuit Digital PLL circuit

1998-03-26

2000-12-05

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

327158, H03D 324, H03L 706

Patent

active

061576905

ABSTRACT:
A PLL circuit comprises a delay control signal generator for increment/decrement of a delay control signal based on a phase lead/lag of an internal clock signal with respect to a reference clock signal, a variable delay circuit for delaying the reference clock signal based on the delay control signal to generate the internal clock signal, and an enable signal generator for retarding the delay control signal generator to increment or decrement the delay control signal for a time length corresponding to the amount of the phase error.

REFERENCES:
patent: 5457718 (1995-10-01), Anderson et al.
patent: 5544203 (1996-08-01), Casasanta et al.
patent: 5790612 (1998-08-01), Chengson et al.
patent: 5910740 (1999-06-01), Underwood

Affiliated with

Also associated with

Rating

Digital PLL circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital PLL circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital PLL circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-968213