Digital PLL circuit

Details Digital PLL circuit Digital PLL circuit

2005-06-10

2010-02-16

Liu, Shuwang (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S294000, C375S354000, C375S327000, C327S141000, C331S018000, C331S040000, C331S044000, C455S260000

Reexamination Certificate

active

07664217

ABSTRACT:
A DPLL circuit is provided for making it possible to inhibit an initial frequency offset during holdover. The DPLL circuit includes a slave oscillator for generating a frequency signal corresponding to the size of a control signal value; a phase difference detection circuit for detecting the difference in phase between the output of said slave oscillator and the inputted reference clock, and outputting a digital signal of the prescribed number of bits corresponding to said detected phase difference; and a holdover unit for generating a correction value based on the output of said phase difference detection circuit, wherein when the holdover is detected, said holdover unit periodically adds the correction value to the output of said phase difference detection circuit to obtain a control value for said slave oscillator.

REFERENCES:
patent: 4553128 (1985-11-01), Pilost
patent: 6072842 (2000-06-01), Janesch et al.
patent: 6687841 (2004-02-01), Marukawa
patent: 6801093 (2004-10-01), Kuwajima
patent: 6968027 (2005-11-01), Fukuhara
patent: 2002/0190764 (2002-12-01), Nichols
patent: 2002-353807 (2002-12-01), None

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