Digital PLL-based data detector for recorded data...

Details Digital PLL-based data detector for recorded data... Digital PLL-based data detector for recorded data...

2000-12-08

2004-08-17

Fan, Chieh M. (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S355000

Reexamination Certificate

active

06778624

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention generally relates to a disc reproduction and/or recording system which at least reproduces recorded data recorded on a disc storage medium such as the optical disc, hard disc, floppy disc, etc. and, more particularly, to an all-digital PLL (phase locked loop) circuit for detecting the recorded data from a data sequence read out of the disc storage medium.
2. Description of the Prior Art
A read data sequence supplied from a recording and reproduction circuit in a disc medium drive usually includes the jitter and is hard to be processed as it is. For this reason, the reproduction of recorded data from a disc storage medium requires a PLL circuit for synchronizing the read data sequence to provide synchronized read data and a sync signal.
The present applicant disclosed an all-digital PLL circuit capable of stable operation at a low voltage of 3.3 V or under in Japanese unexamined patent publication No. 08036836 published Feb. 6, 1996. As the PLL circuit is composed of digital components only, it can be realized as an IC (integrated circuit) or a part of an IC which needs no external discrete component.
The present applicant also disclosed an improved digital PLL-base data detector in Japanese unexamined patent publication No. 09321615 published Dec. 12, 1997. The above-cited documents are hereby incorporated by reference.
However, there are still remaining the following problems in the prior art.
Since there is no limit in the range of frequency adjustable apart from a nominal data rate, input data with a large frequency deviation can cause the proposed PLL circuit to enter into an abnormal synchronization state.
If a series of invalid data are input to the proposed PLL circuit as occurs while the spindle motor is starting or the read/write head is moving, this will cause the numerical processing within the PLL circuit to become abnormal, which may make it uncertain whether the synchronization to a nominal data rate is successfully achieved after the input sequence has recovered valid or regular reproduction data.
The proposed PLL fails to support two or more nominal transmission rates.
SUMMARY OF THE INVENTION
The foregoing problems in the prior art have been solved in accordance with the present invention which provides a digital PLL circuit for use in a disc media reproducer or recorder for receiving input read data read from a disc storage medium and providing an output sync signal and synchronized read data with jitter substantially eliminated. The PLL circuit comprises means for generating a variable-rate internal sync signal, such as a down counter. The length of each period of the internal sync signal is determined as an initial count value supplied at the end of the previous period. A fiducial point is set at a fixed position of each period of the internal sync signal. For each pulse of the input read data, a phase difference between the input read data pulse and the fiducial point of an internal sync signal period concurrent with the input read data pulse is calculated by subtracting one from the other. A fed-back count value is calculated on the basis of the phase difference and phase differences calculated so far. An adder adds the fed-back count value to a given count value to obtain the initial count value. The internal sync signal is frequency-bisected into the output sync signal. The synchronized read data is generated from the input read data and the internal sync signal. The PLL circuit is further provided with a circuit for limiting the fed-back count value to a predetermined range so as to limit the internal sync signal to a desired range.
The PLL circuit may be further provided with a circuit for resetting a predetermined portion of the digital PLL-based circuit during an invalid period when input read data are expected to be invalid to thereby ensuring a normal operation after the invalid period, and/or a circuit for generating, from a given clock signal of a first frequency, a second clock signal of a second frequency different from the first frequency to thereby support a different data rate.
The inventive PLL circuit may be realized by using discrete components or as an IC (integrated circuit) or as a part of an IC. The digital PLL circuit may be incorporated in circuit boards such as various disc drive controllers.


REFERENCES:
patent: 4191976 (1980-03-01), Braun
patent: 5602812 (1997-02-01), Miura et al.
patent: 5793824 (1998-08-01), Burch et al.
patent: 6104682 (2000-08-01), Konishi
patent: 8-36836 (1996-02-01), None
patent: 9-321615 (1997-12-01), None
patent: 278182 (1996-06-01), None

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