Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1998-09-18
2002-06-11
Corrielus, Jean (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C327S152000, C327S153000, C348S512000
Reexamination Certificate
active
06404833
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital phase synchronizing apparatus for synchronizing the phase of a clock signal generated by a signal generator with the phase of an input signal, and more particularly to a digital phase synchronizing apparatus which can efficiently achieve the phase synchronization between a clock signal and input signal without being affected by the signal characteristics of the input signal.
2. Description of the Related Art
Technology for receiving as image data a VGA signal in which a horizontal synchronizing signal and analog data are input from outside, or an NTSC video signal in which a horizontal synchronizing signal is generated internally through synchronous separation have been known.
In such technology, the clock signal of a receiver which receives image data was generated using a high precision, liquid crystal oscillator. The phase of this clock signal was required to conform to the input signal.
Up to now, a PLL (phase locked loop) or the like was used to ensure phase synchronization of the received data signals. However, the use of a PLL has such problems that bit rate is decreased for the reception channel, and a large-sized loop gain stabilizing capacitor as well as a large number of analog circuits are necessary.
To solve the problems, Japanese Patent Laid-open Publication No. 3-151737 discloses a digital phase synchronizing method and arrangement in which a plurality of delayed clock signals are generated by using a plurality of delaying means, these delayed clock signals are compared to the receiver input signal, and which of the plurality of delayed clock signals has a phase closest to the receiver input signal is determined.
However, this conventional technology has the problem that, when an input signal of only “0” or “1” is successively input, and the input signal does not change for a prescribed time, then none of the delayed clock signals is selected, as a result of which phase synchronization is not achieved.
For this reason, when receiving a VGA signal or NTSC signal using this conventional technology, the input signal and clock signal are not synchronized with each other when the input signal does not change for a prescribed time, and therefore, the image cannot be correctly reproduced.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a digital phase synchronizing apparatus which resolves the aforementioned problems and can efficiently achieve the phase synchronization between the clock signal and the input signal without being affected by the signal characteristics of the input signal.
In order to achieve the aforementioned object, the present invention provides a digital phase synchronizing apparatus for synchronizing the phase of a clock signal generated by a signal generator with a phase of an input signal, comprising delayed signal generating means for delaying sequentially clock signals generated by the signal generator and generating a plurality of delayed clock signals having different amount of delay; and selecting means for selecting a delayed clock signal changing at rising edge or falling edge of a horizontal synchronizing signal from among the plurality of delayed clock signals generated by the delayed signal generating means.
With the above configuration, the following effects can be achieved.
1) The phase synchronization of a clock signal and input signal is efficiently achieved without being affected by the signal characteristics of the input signal.
2) The system clock can remain phase synchronized with the horizontal synchronizing signal.
3) Synchronization with the sender of the horizontal synchronizing signal can continually be achieved.
The digital phase synchronizing apparatus according to the present invention may further comprise fine adjusting means for delaying sequentially the delayed clock signal selected by the selecting means, generating a plurality of delayed clock signals having different amount of delay, and selecting a delayed clock signal responding to the fine adjusting operation from among the plurality of delayed clock signals generated.
As a result, the present invention can resolve phase errors between the horizontal synchronizing signal and delayed clock signal selected by the selection means.
Further, the delayed signal generating means may be designed to generate a plurality of delayed clock signals having delays of one or more periods using a delay circuit including at least one or more inverters so as to prevent the collapse of the duty ratio following delay.
Furthermore, the selecting means may be designed to comprise a plurality of flip-flops for detecting status of each of the delayed clock signals at the rising edge or falling edge of the horizontal synchronizing signal; and change point detecting means for receiving detected signals from the plurality of flip-flops and detecting a delayed clock signal having a change point which changes at the rising edge or falling edge of the horizontal synchronizing signal so that the apparatus can efficiently specify a delayed clock signal having a point of change changing at the rising edge or falling edge (hereinafter called change point) of the horizontal synchronizing signal.
The change point detecting means may be designed to detect only the delayed clock signal having the least delay when there are a plurality of delayed clock signals having change point changing at the rising edge or falling edge of the horizontal synchronizing signal so that the apparatus unambiguously specifies a delayed clock signal even in the case where the delay of the delayed clock signal exceeds one period.
The selecting means may be designed to effect pull-up or pull-down of output of each of the flip-flops and excludes the metastable state so the apparatus can prevent the output of the flip-flops being in a metastable state.
The selecting means may be designed to input each of the delayed clock signals generated by the generating means to a plurality of tri-states corresponding to each of the delayed clock signals, and outputs the delayed clock signals input to the prescribed tri-state using an output signal from the change point detecting means so that the apparatus can make uniform the delay times required until signal output, even when the tri-state generating the output is considered.
REFERENCES:
patent: 5022056 (1991-06-01), Henderson et al.
patent: 5533072 (1996-07-01), Georgiou et al.
patent: 5686968 (1997-11-01), Ujiie et al.
patent: 5809095 (1998-09-01), Nakao
patent: 5841482 (1998-11-01), Wang et al.
patent: 6041089 (2000-03-01), Yokomizo
patent: 3151737 (1991-06-01), None
Corrielus Jean
Greer Burns & Crain Ltd.
Komatsu Ltd.
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