Digital phase shift phase-locked loop for data and clock recover

Details Digital phase shift phase-locked loop for data and clock recover Digital phase shift phase-locked loop for data and clock recover

1997-08-19

2000-05-02

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

324 7653, 455260, H03D 324

Patent

active

060581514

ABSTRACT:
A phase-locked loop which is characterized by using two identical phase shifters and programmable UP/DN counters to generate a timing clock having accurate frequency. The clock which is used to recover the received data is made synchronous with the data by adjusting its phase without affecting its frequency. Therefore, frequency drift caused by data jitter of received data does not occur in the phase-locked loop according to the present invention. Besides, since the invention is an all-digital circuit, it is not sensitive to temperature change, voltage variation, or fabricating process fluctuation. Furthermore, it has excellent noise immunity.

REFERENCES:
patent: 4847870 (1989-07-01), Butcher
patent: 5463351 (1995-10-01), Marko et al.
patent: 5479458 (1995-12-01), Tanaka
patent: 5614861 (1997-03-01), Harada
patent: 5633899 (1997-05-01), Fiedler et al.

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