Digital phase relationship lock loop

Details Digital phase relationship lock loop Digital phase relationship lock loop

2011-01-18

2011-01-18

Tseng, Cheng-Yuan (Department: 2184)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C375S376000

Reexamination Certificate

active

07873762

ABSTRACT:
In one embodiment, an apparatus comprises a first clocked storage device operable in a first clock domain corresponding to a first clock signal. The first clocked storage device has an input coupled to receive one or more bits transmitted on the input from a second clock domain corresponding to a second clock signal. The apparatus further comprises control circuitry configured to ensure that a change in a value of the one or more bits transmitted on the input meets setup and hold time requirements of the first clocked storage device. The control circuitry is responsive to a sample history of one of the first clock signal or the second clock signal to detect a phase relationship between the first clock signal and the second clock signal on each clock cycle to ensure the change meets the setup and hold time requirements.

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