Digital phase locked loop with phase selector having...

Details Digital phase locked loop with phase selector having... Digital phase locked loop with phase selector having...

2006-02-21

2006-02-21

Corrielus, Jean (Department: 2637)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S374000, C375S375000

Reexamination Certificate

active

07003066

ABSTRACT:
In one embodiment of the invention, a phase selection unit for generating a recovered clock signal (SCLK), a phase select signal generator generates a phase select signals in response to a FWD signal and a BWD signal from a digital filter. The digital filter asserts the FWD signal if the phase of a SDIN (serial digital input) signal leads the phase of the recovered clock signal, and asserts the BWD signal if the phase of the SDIN (serial digital input) signal lags the phase of the recovered clock signal. A multiplexer receives a number of given clock signals arranged in a predetermined phase order and outputs selected first and second output clock signals, each being one of the given clock signals. A phase interpolator receives the selected first and second output clock signals from the multiplexer to generate the recovered clock signal having a phase that is phase interpolated between the phases of the first and second output clock signals.

REFERENCES:
patent: 5604775 (1997-02-01), Saitoh et al.
patent: 5991341 (1999-11-01), Shin
patent: 6041080 (2000-03-01), Fraisse
patent: 6122336 (2000-09-01), Anderson
patent: 2002/0027886 (2002-03-01), Fischer et al.
patent: 2002/0042836 (2002-04-01), Mallory
patent: 2003/0212930 (2003-11-01), Aung et al.
PCT Publication No. WO 01/69837 A2, published Sep. 20, 2001, Clock Data Recovery Circuit Associated with Programmable Logic Device Circuitry.

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