Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1998-12-28
2002-10-29
Chin, Stephen (Department: 2634)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C327S156000
Reexamination Certificate
active
06473478
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a read channel for a hard disk drive and more particularly to a digital phase-locked loop with phase optimal frequency estimation.
BACKGROUND OF THE INVENTION
Present computer systems typically use hard-disk drive (HDD) systems for mass storage due to their low cost, nonvolatile storage and high capacity. Advances in technology constantly demand improved access times for these HDD systems. Much of the access time limitation is due to a read channel circuit that serves as the physical connection between the HDD and a computer system. Read channel circuits of the prior art frequently employed BiCMOS technology to achieve required access times. The cost and process complexity of these BiCMOS circuits, however, make them an undesirable solution.
These problems with HDD systems are best understood with reference to the physical hard disk of FIG.
1
. The disk is divided into a series of concentric tracks. These tracks may have a density of 5000 to 7000 tracks per inch (TPI). The tracks are arranged in approximately 12 groups or zones of adjacent tracks. Tracks in each zone are written at the same frequency. Since the disk rotates at a constant speed, tracks in the outer zone, for example, are written at a higher frequency than tracks in the inner zone, thereby maintaining a uniform and efficient data density for the entire disk. Each track is divided into data sectors of typically 512 bytes. The tracks are further divided into pie-shaped slices referred to as servo wedges. There are typically 50 to 100 servo wedges in each track. These servo wedges contain control information and are typically written at the same frequency without regard to the track zone.
A HDD read channel operates in read, write and servo modes. The servo mode provides the disk controller with information concerning track number and the magnetic head position on a track. The write loop or synthesizing loop must synthesize different frequencies with reference to a known frequency, typically provided by a crystal oscillator, for the different zones of the HDD. These frequencies are typically synthesized by dividing the reference frequency by M and a variable frequency oscillator (VFO) frequency by N. This VFO is often referred to as a voltage controlled oscillator (VCO). Thus, various ratios of N/M create desired frequencies. A typical analog phase-locked loop (PLL) of the prior art that may be used to synthesize these frequencies is shown in FIG.
2
. The PLL includes a phase detector
11
, a loop filter
13
and a VFO or VCO
15
. This analog PLL, particularly the loop filter, requires considerable circuit area for analog components including capacitors and resistors. Moreover, steady-state power consumption of these analog circuits increases with decreasing response times.
SUMMARY OF THE INVENTION
These problems are resolved by a circuit comprising a register circuit that is arranged to store a control word. A variable frequency oscillator is coupled to receive the control word and produce a clock signal having a current frequency corresponding to the control word. A phase detector is coupled to receive a reference signal and the clock signal. The clock signal has one of a phase lead and a phase lag with respect to the reference signal. The phase detector produces a phase signal having a first state in response to the phase lead and having a second state in response to the phase lag. An estimate circuit is coupled to the register circuit and the phase detector circuit. The estimate circuit produces a next control word corresponding to a next frequency intermediate the current frequency and a frequency corresponding to a transition between the first and second states.
The present invention substantially improves PLL lock time. This improved lock time makes the all-digital approach feasible for time base generation for phase-locked loops.
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patent: 4745372 (1988-05-01), Miwa
patent: 4829391 (1989-05-01), Vargas et al.
patent: 5285483 (1994-02-01), Ogawa et al.
patent: 5511100 (1996-04-01), Lundberg et al.
patent: 5534822 (1996-07-01), Taniguchi et al.
patent: 5731723 (1998-03-01), Chen
patent: 5832048 (1998-11-01), Woodman, Jr.
patent: 6076922 (2000-06-01), Knierim
patent: 6265947 (2001-07-01), Iemmer et al.
Fahrenbruch Shawn A.
Wallberg John L.
Brady III Wade James
Chin Stephen
Fan Chieh M.
Roundtree Robert N.
Telecky , Jr. Frederick J.
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