Digital phase-locked loop with master-slave modes

Details Digital phase-locked loop with master-slave modes Digital phase-locked loop with master-slave modes

2007-07-10

2007-07-10

Fan, Chieh M. (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S276000, C375S215000

Reexamination Certificate

active

10249515

ABSTRACT:
A digital phase locked loop (DPLL) for providing clock synchronization in backplane bus systems has a loop filter with selectable high and low bandwidth modes. The DPLL is thus capable of respectively attenuating or tracking jitter from an input reference clock.

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