Digital phase locked loop with integer channel mitigation

Details Digital phase locked loop with integer channel mitigation Digital phase locked loop with integer channel mitigation

2008-02-01

2011-11-01

Kim, Kevin (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

Reexamination Certificate

active

08050375

ABSTRACT:
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal with a plurality of phases. A switch is coupled to receive the RF clock, and is operative to select one of the plurality of phases. A phase detection circuit is coupled to the switch and is operable to receive a selected phase and to provide digital phase error samples indicative of a time difference between the reference clock and the selected phase.

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