Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2007-11-29
2011-10-25
Bocure, Tesfaldet (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
Reexamination Certificate
active
08045669
ABSTRACT:
In one aspect, a digital PLL (DPLL) operates based on fractional portions of input and output phases. The DPLL accumulates at least one input signal to obtain an input phase. The DPLL determines a fractional portion of an output phase based on a phase difference between an oscillator signal from an oscillator and a reference signal, e.g., using a time-to-digital converter (TDC). The DPLL determines a phase error based on the fractional portion of the input phase and the fractional portion of the output phase. The DPLL then generates a control signal for the oscillator based on the phase error. In another aspect, a DPLL includes a synthesized accumulator that determines a coarse output phase by keeping track of the number of oscillator signal cycles based on the reference signal.
REFERENCES:
patent: 5166642 (1992-11-01), Hietala
patent: 6107890 (2000-08-01), Carson et al.
patent: 6232952 (2001-05-01), Eglit
patent: 6909331 (2005-06-01), Ballantyne
patent: 7023282 (2006-04-01), Humpreys et al.
patent: 7250823 (2007-07-01), Shields
patent: 7274229 (2007-09-01), Humphreys et al.
patent: 7279988 (2007-10-01), Janesch et al.
patent: 7532679 (2009-05-01), Staszewski et al.
patent: 2002/0136341 (2002-09-01), Huh et al.
patent: 2002/0191727 (2002-12-01), Staszewski et al.
patent: 2008/0150642 (2008-06-01), Partridge et al.
patent: 1261134 (2002-11-01), None
patent: 1816741 (2007-08-01), None
Staszewski et al., Phase-Domain All-Digital Phase-Locked Loop, Mar. 2005, IEEE Transactions on Circuits and Systems, vol. 52, No. 53, pp. 159-163.
Kratyuk et al., A Digital PLL With a Stochastic Time-To-Digital Converter, 2006, 2006 Symposium on VLSI Circuits Digest of Technical Papers, pp. 1-2.
Pierce, W, A Novel Approach to Digitally Controlled Phase Locked Loop Tuning Systems, 1982, Consumer Electronics, IEEE Transactions on, vol. CE-28, Issue: 3, pp. 214-219.
Abramovitch, D., Efficient and Flexible Simulation of Phase Locked Loop, Part II: Post Processing and a Design Example, 2008, American Control Conference, pp. 4678-4683.
Staszewski, “Digitally-Intensive Transceiver for GSM/EDGE,” Jun. 7, 2005, Texas Instruments.
International Search Report and Written Opinion—PCT/US2008/085084, International Search Authority—European Patent Office—Nov. 20, 2009.
Ballantyne Gary John
Sun Bo
Bocure Tesfaldet
Moskowitz Larry
QUALCOMM Incorporated
Williams Lawrence B
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