Digital phase locked loop having adaptive bandwidth for pulse st

Details Digital phase locked loop having adaptive bandwidth for pulse st Digital phase locked loop having adaptive bandwidth for pulse st

1996-04-30

1998-08-11

Vo, Don N.

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375376, 370506, 370516, 364724011, H04J 307

Patent

active

057938245

ABSTRACT:
A bandwidth-adaptive digital phase locked loop-based clock control arrangement controls the generation of a read-out clock used for retiming digital data signal interfaced with a synchronous data channel of a communication system, in which pulse-stuffing synchronization is employed to maintain clock synchronization of the digital data signal that is not bit-synchronous with a synchronous digital data channel over which the digital data signal is transported. The bandwidth-adaptive digital phase locked loop includes a loop filter to which the error signal is applied and a phase accumulator, coupled to the output of the loop filter and being operative to stepwise adjust the read-out clock signal. The loop filter has a first scaled path that includes a first, controllably stepped gain stage, and a second scaled path that includes a second, controllably stepped gain stage coupled to a frequency accumulator. The output of the frequency accumulator and the first stepped gain stage are summed and coupled to the phase accumulator. The gain of each of the first and second gain stages is incrementally adjusted in accordance with the magnitude of the error signal.

REFERENCES:
patent: 5200982 (1993-04-01), Weeber
patent: 5390180 (1995-02-01), Reilly
patent: 5402452 (1995-03-01), Powell et al.

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