Digital phase-locked loop for data separation

Details Digital phase-locked loop for data separation Digital phase-locked loop for data separation

1996-01-31

1997-07-29

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375373, 375376, H04L 700, H04L 2536, H04L 2540

Patent

active

056527730

ABSTRACT:
A digital phase-locked loop locks to the reference clock signal in the encoded input data stream and separates the reference clock signal from the actual data signal. The digital phase-locked loop includes a digital oscillator that generates a pulse train with a period continuously adjusted in accordance with time variations in the input data stream so as to maintain the regenerated data in proper phase relationship with the reference clock. The digital phase-locked loop also contains a predict phase generator that generates a predict phase with a fraction part in order to improve the precision of phase adjustment without increasing frequency of the system clock. The circuit also includes a digital low pass filter that generates a first order predict phase, of which the small transient phase variation in the reference clock is removed such that the frequency stability of the recovered reference clock is enhanced. The data window and data regenerator of the circuit generates the data window signal to help separation of reference clock from actual data and regenerated data signal that is more evenly spread in time and more stable in frequency.

REFERENCES:
patent: 4472818 (1984-09-01), Zapisek et al.
patent: 4796280 (1989-01-01), Nesin et al.
patent: 4808884 (1989-02-01), Hull et al.
patent: 4975930 (1990-12-01), Shaw
patent: 5553100 (1996-09-01), Saban et al.

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