Digital phase-locked loop for clock recovery

Details Digital phase-locked loop for clock recovery Digital phase-locked loop for clock recovery

1997-05-01

1999-08-10

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375373, 375360, 375327, H03D 324

Patent

active

059370211

ABSTRACT:
The invention relates to a phase-locked loop delivering a recovered clock signal from a reference clock signal F.sub.ref in which some transitions are missing. The loop includes a first divide-by-M frequency divider receiving the clock F.sub.ref and delivering a signal of frequency F.sub.ref /M; a phase comparator providing a phase error signal from the signal of frequency F.sub.ref /M, and the output signal from a second divide-by-M frequency divider; a divide-by-K frequency divider providing a signal of frequency F.sub.k from a local oscillator signal of frequency F.sub.oL receiving the phase error signal as a control signal; an adder-counter of the division ratio p/q receiving the local oscillator signal of frequency F.sub.oL and delivering a signal of frequency F.sub.o equal to F.sub.oL *p/q; a mixer delivering a signal of frequency F.sub.n equal to F.sub.o -F.sub.k on the basis of signal of frequency F.sub.k and the signal of frequency F.sub.o ; and a divide-by-N frequency divider synchronized by F.sub.oL, receiving the signal of frequency F.sub.n, and delivering a recovered clock to the second divide-by-M frequency divider.

REFERENCES:
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patent: 4803680 (1989-02-01), Rokugo et al.
patent: 5715286 (1998-02-01), Itoh et al.
patent: 5754606 (1998-05-01), Matsuyama et al.
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patent: 5793825 (1998-08-01), Humphreys et al.
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patent: 5825253 (1998-10-01), Mathe et al.
Y. Rokygo et al, "A Digital Phase-Locked Loop for Stuffing Synchronization Systems", Electronics & Communications in Japan-Part I--Communications, vol. 75, No. 4, Apr. 1, 1992, pp. 1-12.

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