Digital phase-locked loop device for synchronizing signal...

Details Digital phase-locked loop device for synchronizing signal... Digital phase-locked loop device for synchronizing signal...

2007-07-17

2007-07-17

Fan, Chieh M. (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S373000, C375S371000, C375S354000, C375S374000, C327S156000

Reexamination Certificate

active

10435787

ABSTRACT:
A phase-locked loop (PLL) device is disclosed. The PLL device includes an interpolator receiving and processing an input signal by an interpolation operation in response to an interpolation timing value to obtain an output signal, a timing error detector in communication with the interpolator for detecting a timing error value of the output signal, a loop filter in communication with the timing error detector for outputting the interpolation timing value to the interpolator in response to the timing error value, and a lock controller in communication with the loop filter for adjusting the interpolation timing value according to a timing quality of the output signal, and providing the adjusted interpolation timing value for the interpolator. A signal generation method for use in the data pick-up device with the aid of the digital phase-locked loop (PLL) device is also disclosed.

REFERENCES:
patent: 4390801 (1983-06-01), Kurata et al.
Ascheid, Gerd, et al., “An All Digital Receiver Architecture For Bandwidth Efficient Transmission at High Data Rates,” IEEE Transactions on Communications, vol. 37, No. 8, Aug. 1989, 804-813.
Farrow, C.W., “A Continuously Variable Digital Delay Element,” 1988 IEEE, 2641-2645.
Schafer, Ronald W., et al., “A Digital Signal Processing Approach to Interpolation,” Proceeding of the IEEE, vol. 61, No. 6, Jun. 1973, 692-702.

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