Digital phase-locked loop compiler

Details Digital phase-locked loop compiler Digital phase-locked loop compiler

2006-12-05

2006-12-05

Ghebretinsae, Temesghen (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S375000, C327S147000, C327S156000

Reexamination Certificate

active

07145975

ABSTRACT:
A digital phase-locked loop compiler includes a pre-divider, a phase digital converter, a digital-to-analog voltage converter, a voltage-control oscillator, a high-frequency oscillator, a post-divider, an out-divider, and a built-in self-tester. The digital phase-locked loop compiler operates in a digital mode and utilizes a preset phase adjusting value to reduce phase-locking time. Moreover, the absence of a low-pass filter in the digital phase-locked loop compiler and the small size of the built-in self-tester greatly reduce the overall area of the digital phase-locked loop compiler.

REFERENCES:
patent: 4151485 (1979-04-01), LaFratta
patent: 5373255 (1994-12-01), Bray et al.
patent: 5815042 (1998-09-01), Chow et al.
patent: 5856762 (1999-01-01), Werker et al.
patent: 5977836 (1999-11-01), Swan et al.
patent: 6366174 (2002-04-01), Berry et al.
patent: 6392496 (2002-05-01), Lee et al.
patent: 6404247 (2002-06-01), Wang
patent: 09-116426 (1997-05-01), None
patent: 11-112336 (1999-04-01), None
A GMSK Modulation using a Delta-Segma Frequency Discriminator-based Synthesizer Wlater t. Bax et al IEEE vol. 36, No. 8 Aug. 2001.

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