Digital phase locked loop circuitry and methods

Details Digital phase locked loop circuitry and methods Digital phase locked loop circuitry and methods

2011-01-11

2011-01-11

Liu, Shuwang (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S375000, C375S373000, C375S374000, C375S354000

Reexamination Certificate

active

07869553

ABSTRACT:
Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.

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