Digital phase-locked loop circuit with filter coefficient genera

Details Digital phase-locked loop circuit with filter coefficient genera Digital phase-locked loop circuit with filter coefficient genera

1994-02-25

1996-11-19

Vu, Kim Yen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375373, 375327, 327156, H03D 324

Patent

active

055770800

ABSTRACT:
A digital phase-locked loop (DPLL) circuit, which achieves a high-precise phase matching between input and output clocks at high speed, irrespective of phase difference between both, is disclosed. The DPLL has a phase comparator for sequentially comparing an input clock with an output clock in phase and outputting phase comparison result signals; a random walk filter for sequentially adding and accumulating the comparison result signals inputted by the phase comparator, discriminating a relative magnitude between the obtained addition data and threshold value information, and outputting a frequency change signal corresponding to the discriminated result and the phase shift amount information; a variable frequency oscillator for generating the output clock and changing frequency of the output clock according to the frequency change signal; and a filter coefficient generating circuit for changing and outputting at least one of the outputted threshold value information and the phase shift amount information according to the phase synchronous status supplied from an operation status detecting circuit.

REFERENCES:
patent: 4791386 (1988-12-01), Shiga
patent: 5057794 (1991-10-01), Shih
patent: 5349309 (1994-09-01), Fujii

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