Digital phase-locked loop circuit

Details Digital phase-locked loop circuit Digital phase-locked loop circuit

1993-11-08

1995-04-25

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375327, 331 1A, 331 25, 331 11, H03D 324

Patent

active

054105730

ABSTRACT:
A digital phase locked loop which incorporates a phase comparator which produces a phase deviation signal having a sinusoidal phase comparison characteristic rather than a sawtooth phase comparison characteristic in order to avoid aliases.

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patent: 5079519 (1992-01-01), Ashby et al.
T. Yagi, Y. Tanimoto, S. Otani, Y. Yoshizawa, H. Ohba & K. Kohno, "Development of Digital Demodulator LSI for Satellite Communication", Institute of Electronics, Information and Communication Engineering Conference, Fall 1990, pp. No. 2-174.
IEEE-IECEJ-ASJ International Conference on Acoustics, Speech, and Signal Processing ICASSP 86, 07.-11.04.1986, Tokyo, JP, vol. 3, pp. 2195-2198, New York, US; S. Ono et al.: `Implementation of a New Type DSP PLL using High Performance DSP DSSP-1`*the whole document.
IEE Transactions on Communications vol. 22, No. 06, Jun. 1974, New York US pp. 751-764 J. Garodnick et al.: `Response of an All Digital Phase-Locked Loop.` *p. 753, left-hand column, paragraph II.8: `Phase Detector Distortion`*.
Patent Abstracts of Japan, vol. 016, No. 134 (E-1185) 6 Apr. 1992 & JP-A-32 96 322 (Fujitsu General Ltd.) 27 Dec. 1991 *abstract*.

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