Digital phase locked loop circuit

Details Digital phase locked loop circuit Digital phase locked loop circuit

1996-02-29

1997-11-11

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375375, H03D 324

Patent

active

056872038

ABSTRACT:
A digital PLL circuit has a data sampling circuit for sampling input data in response to N phase clocks in the direction of time. The phase of the clock corresponding to, among the sampled data, the data in which edges are evenly detected is used as a first phase or reference clock. The successive clocks following the first phase clock are used as a second phase clock to an N-th phase clock. The sampled data are rearranged in synchronism with the first phase clock to the N-th phase clock to turn out first phase to N-th phase sampled data. The first phase to the N-th phase sampled data are latched by the first phase clock. The pattern of data received in bursts is identified every period on the basis of the latched first to N-th phase data. Among the latched first to N-th sampled data, the data to be identified are selected. These data are retimed in synchronism with the first phase clock so as to output a phase clock signal.

REFERENCES:
patent: 4841551 (1989-06-01), Avaneas
patent: 4972444 (1990-11-01), Melrose et al.
patent: 5034967 (1991-07-01), Cox et al.
patent: 5259005 (1993-11-01), LaRosa et al.
patent: 5272391 (1993-12-01), Ampe et al.
patent: 5349613 (1994-09-01), Dijkhof
patent: 5371766 (1994-12-01), Gersbach et al.

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