Digital phase-locked loop circuit

Details Digital phase-locked loop circuit Digital phase-locked loop circuit

1996-12-19

1999-07-13

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375375, 331 57, 331 25, 331 1A, H03D 324

Patent

active

059237155

ABSTRACT:
A digital PLL circuit is provided that has a frequency comparator circuit for comparing the frequencies of an output clock signal and a reference clock signal to generate frequency comparator information. A delay control circuit generates a predetermined digital signal based on the frequency comparator information, and a clock signal generating circuit generates the output clock signal of the PLL circuit. The clock signal generating circuit changes the oscillation frequency of the output clock signal in response to the predetermined digital signal generated by the delay control circuit. According to a preferred embodiment, the number of connected delay stages in a variable delay circuit (of the clock signal generating circuit) is controlled on the basis of the output of the frequency comparator circuit. Additionally, variable load capacitance circuits in the variable delay circuit are controlled mainly on the basis of the output of the frequency comparator. In this way, the present invention provides a digital PLL having small jitter and a high accuracy, without requiring a complicated control algorithm.

REFERENCES:
patent: 5347234 (1994-09-01), Gersbach et al.
patent: 5487093 (1996-01-01), Adresen et al.
patent: 5687202 (1997-11-01), Eitrheim

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