Digital phase locked loop capable of suppressing jitter

Details Digital phase locked loop capable of suppressing jitter Digital phase locked loop capable of suppressing jitter

1999-01-14

2002-05-14

Bocure, Tesfaldet (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S375000, C327S158000, C331S057000

Reexamination Certificate

active

06389091

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a digital phase locked loop which keeps an output signal exactly in phase and frequency with a reference signal, particularly, relates to a digital phase locked loop which is used for an LSI, such as an ASIC (application specific integrated circuit).
A conventional digital phase locked loop comprises a phase comparator which compares phase and frequency of a feedback signal with those of an reference signal supplied from an outer circuit. The phase comparator produces an error signal which is representative of frequency difference between the feedback signal and the reference signal. A low pass filter is connected to the phase comparator and filters the error signal to produce an analog control signal. A voltage controlled oscillator is connected to the low pass filter and the phase comparator and produces an output signal having a frequency which depends on the analog control signal. The output signal is supplied to, for example, an inner circuit of an LSI and to the phase comparator as the feedback signal.
The voltage controlled oscillator has a plurality of delay elements which is connected to one another in a ring so as to form a ring oscillator. Each of delay elements has a delay which is changed by the analog control signal. A total delay of the delay elements decides the frequency of the output signal.
The conventional digital phase locked loop has a defect that the output signal is greatly influenced by noise added to the analog control signal. The noise brings jitters on the output signal. In addition, the conventional digital phase locked loop has a large size because it needs the low pass filter.
Another conventional digital phase locked loop comprises a phase comparator which compares phase and frequency of a feedback signal with those of a reference signal supplied from an outer circuit. The phase comparator produces an up/down signal for increasing/decreasing the frequency of the feedback signal. A control circuit is connected to the phase comparator and produces the digital control signal in response to the up/down signal. An oscillator is connected to the control circuit and the phase comparator and produces an output signal which has a frequency controlled by the digital control signal. The output signal is supplied to an inner circuit of an LSI and to the phase comparator as the feedback signal.
The oscillator has a plurality of delay elements which are connected one another. Each of the delay elements has a fixed delay. The delay elements are selectively activated by the digital control signal. Activated delay elements forms a ring oscillator. A total delay of the activated delay elements decides a frequency of the output signal.
The conventional digital phase locked loop has a fault that the frequency of the output signal is discontinuously changed by the digital control signal. This increases jitters added on the output signal. Moreover, the conventional digital phase locked loop has another fault that it is necessary to control a timing of activation/inactivation of the delay elements. In addition, the conventional digital phase locked loop uses large electricity.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a digital phase locked loop which is capable of suppressing jitters on an output signal.
It is another object of this invention to provide a digital phase locked loop which has a small size and uses small electricity.
It is still another object of this invention to provide a digital phase locked loop that it is easy to control.
Other object of this invention will become clear as the description proceeds.
On describing the gist of this invention, it is possible to understand that a digital phase locked loop keeps an output signal exactly in phase and frequency with a reference signal.
According to the gist of this invention, the digital phase locked loop comprises a phase comparator which compares a feedback signal with the reference signal in phase and frequency to produce an error signal representative of frequency difference between the feedback signal and the reference signal. A controller is connected to the phase comparator to produce a plurality of digital control signal sets in response to the error signal. An oscillator has a plurality of delay elements which are connected to the controller and connected to one another in a loop. Each of the delay elements has a delay which is controlled by one of the digital control signal sets. The oscillator produces the output signal which has a frequency decided by a total delay of the delay elements. A feedback line is connected between the oscillator and the phase comparator to feed back the output signal to the phase comparator as the feedback signal.
According to another gist of this invention, a delay element is used in a ring oscillator together with the preceding and the following delay elements. The delay element has a delay which is controlled by a digital control signal set. The digital control signal set includes first and second groups of digital control signals. The delay element comprises an input terminal which is connected to the preceding delay element. An output terminal is connected to the following delay element. A plurality of first P type transistors have first sources supplied with source voltage, first drains, and first gates being for receiving the first group. A second P type transistor has a second source connected to the first drains, a second drain connected to the output terminal, and a second gate connected to the input terminal. A plurality of first N type transistors have third sources connected to the ground, third drains, and third gates being for receiving the second group. A second N type transistor has a fourth source connected to the third drains, a fourth drain connected to the output terminal, and a fourth gate connected to the input terminal.
According to still another gist of this invention, a delay element being for use in a ring oscillator together with the preceding and the following delay element. The delay element has a delay which is controlled by a digital control signal set. The digital control signal set includes third and fourth groups of digital control signals. The delay element comprises an input terminal is connected to the preceding delay element. An output terminal is connected to the following delay element. A third P type transistor has a fifth source supplied with source voltage, a fifth drain, and a fifth gate connected to the input terminal. A plurality of fourth P type transistors have sixth sources connected to the fourth drain, sixth gates connected to the output terminal, and sixth drains being for receiving the third group. A third N type transistor has a seventh source connected to the ground, a seventh drain, and a seventh gate connected to the input terminal. A plurality of fourth N type transistors have eighth sources connected to the seventh drain, eighth drains connected to the output terminal, and eighth gates being for receiving the fourth group.


REFERENCES:
patent: 5077529 (1991-12-01), Ghoshal et al.
patent: 5331294 (1994-07-01), Watanabe et al.
patent: 5347234 (1994-09-01), Gersbach et al.
patent: 5389898 (1995-02-01), Taketoshi et al.
patent: 5438300 (1995-08-01), Saban et al.
patent: 5451911 (1995-09-01), Colvin et al.
patent: 5687202 (1997-11-01), Eitrheim
patent: 5748125 (1998-05-01), Cederbaum et al.
patent: 5771264 (1998-06-01), Lane
patent: 6271730 (2001-08-01), Abe et al.
patent: 0 639 003 (1995-02-01), None
patent: 0 712 204 (1996-05-01), None
patent: 0 792 019 (1997-08-01), None
patent: 3-153124 (1991-07-01), None
patent: 3-206726 (1991-09-01), None
patent: 5-315899 (1993-11-01), None
patent: 9-214334 (1997-08-01), None
patent: 9-275332 (1997-10-01), None

Affiliated with

Also associated with

No associations

Rating

Digital phase locked loop capable of suppressing jitter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital phase locked loop capable of suppressing jitter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital phase locked loop capable of suppressing jitter will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2816632