Digital phase-locked loop arrangement for use in a desynchronize

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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375371, H03D 324, H04L 700

Patent

active

054715113

ABSTRACT:
A digital phase locked loop arrangement is used in a desynchronizer demapping a plesiochronous stream from a synchronous bitstream is disclosed to remove jitter due to overhead gapping from the plesiochronous stream. To this end the part of the synchronous bitstream constituting the plesiochronous stream is written into a buffer memory (BUFF), the write address (WRADDR) of which is incremented at the rate of this plesiochronous part. The read address (RDADDR) for the buffer memory (BUFF) is derived from the write address (WRADDR) in the digital phase locked loop arrangement. Herein, a negative feedback for byte justifications in the synchronous bitstream and a positive feedback for bit justifications therein is provided so that byte justifications give rise to a lower change in the incrementing rate of the read address (RDADDR) but of longer duration, whereas bit justifications give rise to an increased change in this incrementing rate but of shorter duration.

REFERENCES:
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patent: 5202904 (1993-04-01), Kamada
patent: 5272703 (1993-12-01), Peters
patent: 5285206 (1994-02-01), Peters et al.
patent: 5349310 (1994-09-01), Rieder et al.
"Design and Performance Verification of a SONET-to-DS3 Desynchronizer", R. Hamlin, Jr., Globecom '91, 22.7.1-22.7.4, pp. 761-764.
"Transmission Networking: SONET and the Synchronous Digital Hierarchy", M. Sexton et al, Artech House, Norwood Mass. 1992, pp. 104-105.

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