Digital phase locked loop

Details Digital phase locked loop Digital phase locked loop

1994-06-30

1996-03-26

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

327156, 327159, 327160, H03D 324

Patent

active

055027512

ABSTRACT:
A digital oscillator is synchronized to a master clock by comparing the master clock to an output of the digital oscillator by providing both to a first register which enables a counter. The counter increments while enabled until cleared. The output of the counter is then compared with a stored signal. Depending upon the match with the stored signal, the output of the digital oscillator is either slowed, advanced or maintained. The output from the digital oscillator is then fed back to an input of the digital phase locked loop.

REFERENCES:
patent: 4688094 (1987-08-01), Tanabe et al.
patent: 4964117 (1990-10-01), Shier

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