Digital phase locked circuit capable of dealing with input...

Details Digital phase locked circuit capable of dealing with input... Digital phase locked circuit capable of dealing with input...

2008-07-08

2008-07-08

Odom, Curtis (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S371000, C375S372000, C375S373000, C375S374000, C375S375000, C327S147000, C327S148000, C327S149000, C327S150000, C327S151000, C327S156000, C327S157000, C327S158000, C327S159000

Reexamination Certificate

active

07397882

ABSTRACT:
A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if the input clock signal is supplied in a burst fashion. A phase comparing part compares the phase of the output clock signal with the phase of the input clock signal. A phase comparison result detecting part outputs an INC/DEC request signal for controlling a division operation based on a phase comparison signal. An execution rate computing part computes a phase difference between the input clock signal and the output clock signal based on the INC/DEC request signal and outputs an execution rate corresponding to the phase difference. A clock generating part controls a division operation for the master clock signal in accordance with the INC/DEC request signal and changes phase absorption speed of the output clock signal in accordance with the execution rate.

REFERENCES:
patent: 4030045 (1977-06-01), Clark
patent: 5781054 (1998-07-01), Lee
patent: 6154071 (2000-11-01), Nogawa
patent: 6233297 (2001-05-01), Itoh
patent: 6920622 (2005-07-01), Garlepp et al.
patent: 2003/0076911 (2003-04-01), Kobayashi et al.
patent: 6-53821 (1994-02-01), None
patent: 7-86926 (1995-03-01), None

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