Digital phase lock loop with control for enabling and disabling

Details Digital phase lock loop with control for enabling and disabling Digital phase lock loop with control for enabling and disabling

1998-11-19

2000-11-28

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375327, 327150, 329307, H03D 324

Patent

active

061545120

ABSTRACT:
The invention relates to methods and apparatus for synchronizing a local data clock with timing information from received data, during a fraction of a frame period. The apparatus includes a transition detect unit, a digital phase comparator, a phase regulator, and a control unit, for detecting the bit transitions of received data, determining the phase difference between timing information and a local data clock, advancing or retarding the local data clock, and enabling and disabling the synchronization in accordance with a predetermined rate.

REFERENCES:
patent: 4085288 (1978-04-01), Viswanathan
patent: 4166979 (1979-09-01), Waggener
patent: 4280099 (1981-07-01), Rattlingourd
patent: 4972444 (1990-11-01), Melrose et al.
patent: 5081655 (1992-01-01), Long
patent: 5278702 (1994-01-01), Wilson et al.
patent: 5398263 (1995-03-01), Vanderspool, II et al.
patent: 5920600 (1999-07-01), Yamaoka et al.

Affiliated with

Also associated with

Rating

Digital phase lock loop with control for enabling and disabling does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital phase lock loop with control for enabling and disabling , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital phase lock loop with control for enabling and disabling will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1733179