Digital phase-lock loop network

Details Digital phase-lock loop network Digital phase-lock loop network

1995-12-11

1998-08-04

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

370208, H03D 324

Patent

active

057906157

ABSTRACT:
A digital phase-lock loop network that provides input and output clock signals to a digital data receiving system generally, and particularly to a data buffer contained therein, is disclosed. The digital phase-lock loop network provides bit-clock synchronization using a fixed input clock and an output clock having a variable frequency that is adjusted to correspond to the average input rate of the data samples into the data buffer. The digital phase-lock loop network allows the data buffer to be operated as a temporary storage device maintaining a nominal number of data samples therein at all times by avoiding any overflow and underflow data handling conditions that may otherwise cause loss of data. The digital phase-lock loop network of the present invention is particularly suited for the Eureka-147 system which has become a worldwide standard for digital audio broadcasting (DAB) technology.

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Digital Sound Broadcasting to Vehicular, Portable, and Fixed Receivers for BSS (Sound) in the frequency range 500-3000 MHz, Document 10/30-E, 10 Dec. 1991.
Digital Sound Broadcasting to Mobile Receivers, Bernard Le Floch, Roselyne Halbert-Lassalle, Damien Castelain, IEEE Transactions on Consumer Electronics, vol. 35, #3 Aug. '89.

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