Digital phase lock loop having frequency offset cancellation cir

Details Digital phase lock loop having frequency offset cancellation cir Digital phase lock loop having frequency offset cancellation cir

1995-03-21

1996-08-13

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 10, 331 17, 331 1A, 364162, H03D 324

Patent

active

055464335

ABSTRACT:
A phase-lock loop (PLL) circuit can be locked on to a synthesizer frequency without decreasing the available range of the frequency differences which the PLL circuit can accommodate during a data receive mode. An analog-to-digital conveyer (ADC) receives an analog input signal and responds to a periodic clock signal by providing a corresponding digital output signal. A phase comparator is coupled to receive the ADC digital output signal and to provide a phase error signal which is representative of a phase error in the digital output signal. A filter accumulates the value of the phase error signal into a filter first register to generate a primary frequency error value. The filter further includes a filter second register for holding a secondary frequency error value (e.g., a value which corrects for an offset between a synthesizer frequency and the PLL free-running frequency). A primary digital-to-analog converter (DAC) converts a primary filter output value, which includes the primary frequency error value, to a corresponding primary analog output signal. A secondary DAC converts a secondary filter output value, which includes the secondary frequency error value from the filter second register, to a corresponding secondary analog output signal responsive to the secondary filter output value. The primary analog output signal and the secondary analog output signal the combined to provide a control signal to an oscillator that provides the clock signal to the ADC. The frequency of the clock signal is controlled by the control signal.

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