Digital phase lock loop for jitter filtering and frequency offse

Details Digital phase lock loop for jitter filtering and frequency offse Digital phase lock loop for jitter filtering and frequency offse

1994-07-15

1995-11-21

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375374, 375373, 331 1A, 331 14, H03D 324, H03L 700

Patent

active

054694787

ABSTRACT:
A digital phase lock loop for producing an output signal based on an input signal which is subject to jitter and frequency offset. The output signal follows the center of the jitter on the input signal to produce a jitter-filtered signal which compensates for the frequency offset. The digital phase lock loop includes a phase detector, a pulse scaler counter, a phase error counter and a first digitally controlled oscillator. The phase detector detects a phase difference between the input signal and the output signal and outputs up or down pulses depending on the phase difference. The pulse scaler counter increments an up/down counter when an up pulse is received from the phase detector, and decrements the up/down counter when a down pulses is received from the phase detector. When the up/down counter overflow or underflows, a correction pulse is output. The phase error counter resets during every cycle of the input and output signals. The phase error counter will increment an up counter when an up or down pulse is received from the phase detector. When the up counter overflows, a correction pulse is output. The first digitally controlled oscillator produces and outputs the output signal. The first digitally controlled oscillator adjusts the phase of the output signal depending on the correction pulses received from the pulse scaler counter and the phase error counter.

REFERENCES:
patent: 5077529 (1991-12-01), Ghoshal et al.
patent: 5200982 (1993-04-01), Weeber
patent: 5258877 (1993-11-01), Leake et al.
patent: 5272730 (1993-12-01), Clark
patent: 5329560 (1994-07-01), Rastegar et al.
FDDI Hybrid Ring Control (HRC) Draft Proposed American National Standard; Points of Contact: Gene Milligan (X3T9.5 Chairman) and Floyd Ross (X3T9.5 Vice Chairman; May 28, 1992.

Affiliated with

Also associated with

Rating

Digital phase lock loop for jitter filtering and frequency offse does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital phase lock loop for jitter filtering and frequency offse, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital phase lock loop for jitter filtering and frequency offse will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1143987