Digital phase lock loop circuit

Details Digital phase lock loop circuit Digital phase lock loop circuit

2005-09-13

2005-09-13

Fan, Chieh M. (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S355000

Reexamination Certificate

active

06944251

ABSTRACT:
The digital phase locked loop circuit according to the invention includes a GAC circuit (4) for calculating the average frequency of the phase locked sampling clock signals in selected channels and for feeding back the calculated average to the phase locked loop. The GAC circuit (4) includes comparators (111˜118) for comparing the frequency of the sampling clock signals in each channel with an allowable frequency range and for outputting a frequency error signal with respect to any channel in which the frequency of the sampling clock signals is outside the allowable frequency range.

REFERENCES:
patent: 5442315 (1995-08-01), Hutchins
patent: 5572157 (1996-11-01), Takashi et al.
patent: 5754138 (1998-05-01), Turcotte et al.
patent: 5903484 (1999-05-01), Tsujihashi
patent: 6118745 (2000-09-01), Hutchins et al.
patent: 6246733 (2001-06-01), Hutchins
patent: A-6-325506 (1994-11-01), None
patent: A-10-40079 (1998-02-01), None

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