Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1996-02-28
1998-09-22
Chin, Stephen
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
375360, 375361, 327159, H03D 324, H04L 702
Patent
active
058126198
ABSTRACT:
A digital phase lock loop and system for data extraction and clock recovery of Ethernet data reduces power consumption, area, and noise sensitivity. In one aspect, a digital phase lock loop (PLL) includes a data extraction and end of transmission delimiter (ETD) circuit, an edge detection comparator coupled to the data extraction and ETD circuit, an up/down counter coupled to the edge detection comparator, and a phase adjustment oscillator coupled to the counter and to the data extraction and ETD circuit for producing phase adjustments in a reference clock signal in accordance with shifts in the frequency of the data. In a system aspect of the present invention, the system receives the data in a digital PLL circuit, and adjusts a phase of a reference clock and a sample clock to track transitions in the data through the digital PLL.
REFERENCES:
patent: 4231071 (1980-10-01), Anderson
patent: 4546486 (1985-10-01), Evans
patent: 4608702 (1986-08-01), Hirzel et al.
patent: 5168511 (1992-12-01), Boles
patent: 5276716 (1994-01-01), Wincn
patent: 5436937 (1995-07-01), Brown et al.
patent: 5504751 (1996-04-01), Ledzius et al.
Advanced Micro Devices , Inc.
Chin Stephen
Deppe Betsy L.
LandOfFree
Digital phase lock loop and system for digital clock recovery does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digital phase lock loop and system for digital clock recovery, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital phase lock loop and system for digital clock recovery will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1631015