Digital phase lock loop

Details Digital phase lock loop Digital phase lock loop

2000-03-24

2004-11-30

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S150000, C327S153000, C327S159000, C348S505000, C348S522000, C348S537000

Reexamination Certificate

active

06826247

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to systems that utilize phase lock loops, and more particularly to a system that utilizes a digital phase lock loop.
2. Description of Related Art
A variety of electronic devices, such as computers, monitors, flat panel displays, wireless communication devices, cellular phones, high speed two-way digital transceivers, and paging devices, to name just a few, utilize a plurality of synchronous signals, e.g., clock signals, vertical-synch and horizontal-synch signals, spread spectrum and digital wireless communication signals, etc., that are phase synchronized with other signals associated with such devices. A key part of the synchronization function is usually handled by a phase-locked loop circuit. A phase comparator or phase detector constitutes a main functional component in the signal phase synchronization process.
Phase lock loop circuits have been conventionally manufactured using analog circuit construction. An analog phase detector in a phase lock loop produces an analog output signal, for example a voltage signal, to indicate a phase difference. In a phase-locked loop, for example, this analog signal may control a frequency source, such as a voltage controlled oscillator (VCO). High precision adjustments in the frequency signal output from the VCO may depend on very precise, custom analog circuit design and components for an analog phase detector.
Analog phase lock loops, as with most analog circuit designs, suffer from sensitivity to noise signals, temperature variability, and manufacturing process variations. Further, to increase the precision of an analog circuit may require significant additional component cost and multiple fabrication iterations. Furthermore, analog circuit designs tend to require large circuit real estate such as to implement a precision phase lock loop circuit. Additionally, as with any analog circuit design, the design time tends to be long in order to port a design to a new circuit manufacturing process. To transfer an analog phase lock loop to a new manufacturing process, the design effort and risk are substantially the same as the original design.
With the increasing popularity of digital circuits in all of the aforementioned devices, the trends are 1) toward smaller and more compact devices requiring smaller real estate circuit designs, 2) continuous improvements in circuit manufacturing technologies requiring easily adaptable circuit designs for new technologies, and 3) increasing demand for higher precision signal phase synchronization. It is unfortunate, therefore, that there is not available a high precision all digital phase lock loop circuit for such electronic devices and that overcomes the disadvantages of the prior art as discussed above.
Thus, there is a need to overcome the disadvantages of the prior art as discussed above.


REFERENCES:
patent: 5218314 (1993-06-01), Efendovich et al.
patent: 5319681 (1994-06-01), Meyer
patent: 5448191 (1995-09-01), Meyer
patent: 5563531 (1996-10-01), Meyer
patent: 5659585 (1997-08-01), Meyer
patent: 5841430 (1998-11-01), Kurikko
patent: 5936678 (1999-08-01), Hirashima
patent: 6002279 (1999-12-01), Evans et al.
patent: 6122336 (2000-09-01), Anderson
patent: 6628276 (2003-09-01), Elliott
patent: WO 99/67882 (1999-12-01), None
patent: WO 00/14879 (2000-03-01), None
Osicom Technologies Inc. Technical Staff, “Direct-Digital Frequency Synthesis . . . a basic tutorial” pp. 1-19.
Mark G. Johnson et al., “A Variable Delay Line PLL for CPU-Coprocessor Synchronization”, Reprinted from IEEE Journal of Solid-State Circuits, vol. SC-23, Oct. 1988, pp. 333-338.
Jeff Sonntag et al., 1990 IEEE International Solid-State Circuits Conference Digest of Technical Papers, First Edition Feb. 1990,. Session 11: High-Speed Communication IC's, FAM 11.5: “A Monolithic SMOS 10MHz DPLL for Burst-Mode Data Retiming”, pp 194-195.
Ian A. Young et al., “A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors”, Reprinted from IEEE Journal of Solid-State Circuits, vol. SC-27, Nov. 1992, pp. 339-346.
I.N. Gurevich et al., Radio-Electronic Circuts and Devices, “Controllable Delay Devices in Two-Level Frequency-Synthesis Systems”, Telecommunications and Radio Engineering 48(5). 1993, pp. 61-68.
Dina L. McKinney et al., “Digital's DECchip 21066: The First Cost-focused Alpha AXP Chip”, vol. 6 No. 1, Winter 1994, Digital Technical Journal, pp. 66-77.
Jim Dunning et al., “An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors”, IEEE Journal of Solid-State Circuits, vol. 30, No. 4, Apr. 1995, pp. 412-422.
Yoshinori Okajima et al., “Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface”, IEICE Trans. Electron. vol. E79-C, No. 6 Jun. 1996, pp. 798-807.
Stefanos Sidiropoulos et al., “A Semidigital Dual Delay-Locked Loop”, IEEE Journal of Solid-State Circuits, vol. 32, No. 11, Nov. 1997, pp. 1683-1692.
European Search Report dated Jun. 10, 2003 for European Patent Application No. 01302073.

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