Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1997-12-10
2000-11-14
Chin, Stephen
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
375376, 331 25, 331 57, 327159, H03D 324
Patent
active
061480525
ABSTRACT:
A DPD (digital phase error) circuit for measuring the phase skew between a first and a second clock signal for use in a variety of control systems and more particularly for use in DPLL (digital phase-locked loop) synchronizers. The DPD includes an ROG (ring oscillator generator) which has a string of inverter gates forming an RO (ring oscillator) and a ring counter. The ring counter operates to monitor the time elapsed from the occurrence of a reset clock signal edge by recording the number of oscillation periods of the RO. The RO and ring counter are coupled to an ROC (ring oscillator capture) unit which operates to capture the state of the RO and ring counter for every occurrence of a respective first clock signal edge and second clock signal edge so as to accurately evaluate the time elapsed since the occurrence of the preceding reset clock signal edge. These measurements are routed to a CU (control unit) where they are processed to determine the actual phase error between the first and second clock signals. For each capture effected in the ROC, a highly accurate calibration signal generated to have a fixed phase deviation from the reset clock signal is received for capturing state of the RO and ring counter to determine the average inverter propagation delay of the inverter gates forming the RO and accordingly calibrate each phase error in accordance with the proper average inverter propagation delay.
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Chin Stephen
Ha Dac V.
Nortel Networks Corporation
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