Digital phase alignment apparatus in consideration of metastabil

Details Digital phase alignment apparatus in consideration of metastabil Digital phase alignment apparatus in consideration of metastabil

1998-08-21

2000-02-29

Ghebretinsae, Temesghen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375371, 370516, H03D 324

Patent

active

060318864

ABSTRACT:
The present invention provides a digital phase alignment which to select the clock whose the transition is occured in the close vicinity of a center of the input data unit interval, the rising transition or falling transition of data are detected, as a result, to generate the synthetic clock retiming data upon detecting the transition of data having a random bit column, the retiming clock is reached in the center of eye pattern of data, compared with a single directional transition is detected.

REFERENCES:
patent: 4814879 (1989-03-01), McNeely
patent: 5533072 (1996-07-01), Georgiou et al.
A 45-Mbit/s CMOS VLSI Digital Phase Aligner; Robert R. Cordell; 1988.

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