Digital peak-hold circuit

Details Digital peak-hold circuit Digital peak-hold circuit

1986-06-26

1987-08-11

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307359, 324103P, 328151, H03K 5153, G01R 1904

Patent

active

046863907

ABSTRACT:
A digital peak-hold detector for determining the peak value of an input analog voltage to be displayed on a multiple-element display device detects when the value of the input analog voltage exceeds the value of a ramp-like waveform generated from a counter which repetitively counts down from a number equal to the total number of display elements to zero to generate a compare signal. A control circuit strobes the count corresponding to the peak value into a storage register when the value of the input analog voltage exceeds the current peak value in the storage register. A digital comparator compares the current peak value from the storage register with the repetitive count from the counter and outputs an update signal when the value of the count is greater than the current peak value. The update signal is combined with the compare signal by the control circuit to make the determination whether to update the current peak value. A time delay circuit causes the control circuit to clear the storage register to generate a new peak value when the current peak value is not updated within a predetermined period of time.

REFERENCES:
patent: 4204260 (1980-05-01), Nysen
patent: 4560940 (1985-12-01), van der Schans
M. O. Palva, "Detect and Hold an Analog-Signal Peak with an A/D Converter and an 8-Bit Latch", Electronic Design 16, vol. 26, Aug. 2, 1978, p. 92.

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