Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2000-04-11
2002-04-02
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S083000
Reexamination Certificate
active
06366125
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior French Patent Application No. 99-04609, filed Apr. 13, 1999, the entire disclosure of which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to digital signals, and more specifically to digital signal shaping for digital data transmissions between different units of data processing, instrumentation, or communications equipment.
2. Description of Related Art
A digital signal has the form of a voltage or current that alternates between two possible levels: a “high” level and a “low” level. A binary value (i.e., 0 or 1) is attributed to each of these two states. The transitions between the two levels of the signal form a corresponding series of binary values. This series of binary values carries information transmitted with the signal between a source and one or several reception points. The binary signals of a given protocol must conform to a specification which establishes their electrical characteristics such as the voltage or current levels that correspond to the logic values 0 and 1, the rise and fall times from one level to another, and the duration of a logic state. It is essential that the specification is rigorously complied with in order to correctly recognizing the exchanged data.
FIG. 1
shows a portion of a binary signal in the form of a voltage pulse (shown on the Y axis) that changes over time (shown on the X axis). An element of binary information 1 or 0 is represented by the presence of a voltage at the high level, which is determined by Vcc, or the low level, which is set at 0 V. These voltage levels must exist during predetermined time periods t
H
and t
B
, respectively. A transition from the low level to the high level (or “rising edge”) takes a relatively short finite time t
m
. The same applies for the time t
d
for a transition from the high level to the low level (or “falling edge”). In the example of
FIG. 1
, the binary signal is symmetrical insofar as the times t
H
and t
B
of the high and low levels are identical, as are the transition times t
m
and t
d
between those levels.
When a binary signal is to be transmitted by a cable over distances beyond a few centimeters, and possibly a few meters, the electrical characteristics of the cable in terms of resistance, capacitance, and induction, which are proportional to its length, create a load which tends to attenuate and modify the shape of the voltage or current waveforms. To prevent this phenomenon from causing a loss of transmission quality, it is required to send the binary signal through a relatively low impedance output stage which can switch rapidly between the levels.
FIG. 2
shows an one such conventional output stage.
The output stage
10
includes an input terminal E which receives the binary signal before it is appropriately shaped for transmission along a line. For example, the binary input signal can come from a large-scale integration logic circuit. In general, the output stages of such circuits are not capable of driving a lossy transmission line. The purpose of the output stage is to apply this input signal onto the transmission line with a low output impedance. The input E is connected to a logic inverter
12
whose output is connected to each gate of first and second complementary MOS transistors
14
and
16
. These transistors are connected in series between a supply voltage line Vcc and ground to form another inverter.
The first and second transistors
14
and
16
are PMOS and NMOS type transistors, respectively. The source of the first transistor
14
is connected to the voltage line Vcc and its drain is connected to the source of the second transistor
16
. The drain of the second transistor
16
is connected to a 0 V (or ground) line. The output S of the output stage
10
is located at a connection node between the first and second transistors
14
and
16
. This output S drives a transmission line
18
which exhibits a capacitive loss symbolized by a capacitor C
1
(shown in dotted lines) that connects the transmission line
18
to ground.
The first and second transistors
14
and
16
are specially designed to deliver or absorb a high current. To this end, they possess a conduction channel of relatively large dimensions, which thus provides a low resistance. The presence of the logic inverter
12
serves to establish a double inversion of the digital signal supplied at the input (i.e., in combination with the inverter formed by transistors
14
and
16
). As a result, the signals at the input E are reproduced with the same polarity at the output S. When the digital signal at the node NG connecting the gates of transistors
14
and
16
is at 0 V (which corresponds to a high level at input E), the second transistor
16
is OFF while the first transistor
14
is switched ON. Accordingly, the output S is connected to the supply voltage line Vcc via transistor
14
. Conversely, when the digital signal at node NG is at the supply voltage level Vcc, the first transistor
14
is OFF and the second transistor
16
is switched ON. Thus, the output S is connected to ground via transistor
16
.
The voltage level transitions at the output S (either to the high or to the low state) depend on the characteristics of the first
14
and second
16
transistors. In particular, these transistors determine the rise and fall times of the digital signal on the transmission line
18
. Generally, it is desirable for the rise and fall times of the digital signal be the same (i.e., for the rising and falling edges of the signal to have the same shape as shown in FIG.
1
). This implies identical characteristics for transistors
14
and
16
, which are respectively of the PMOS and NMOS types. In particular, the critical characteristics are the switching thresholds of the transistors (i.e., the voltage level required to set the transistors into saturation) and the channel resistances.
However, in practice, PMOS and NMOS transistors cannot be rigorously identical with regard to these characteristics. In particular, the threshold voltage is determined at the fabrication stages, which are different depending on whether the transistor is a PMOS or NMOS transistor. Accordingly, the rising and falling edges cannot be perfectly symmetrical with an output stage of the type shown in FIG.
2
. Moreover, in practice, there is a difference in the above-mentioned characteristics between two theoretically identical output stages
10
because of inevitable dispersions in the fabrication processes. This adds to the lack of symmetry due to the inherent differences between the PMOS and NMOS transistors when the digital signal is sent in the form of differential pairs. According to such a transmission mode, the digital data is sent on each of two transmission channels (for example, a pair of wires).
FIG. 3
shows the superposition of the theoretical shape of each signal of the digital signal pair of a differential pair transmission. These signals SP
1
and SP
2
are of mutually opposite levels, with one being fixed as the inverse of the other. In this example, the high and low levels of the signals are respectively at voltages Vcc and 0 V. A protocol establishes which of the two signals SP
1
or SP
2
is indexed to the logic levels of the transmitted data, and the other signal serves to establish the reference for the potential difference. The rising edges F
A
and the falling edges F
D
of the two signals are symmetrical, so their crossover points at the level transitions are always located at the median level (i.e., at ½ Vcc in this example).
Data transmission in the form of differential pairs occupies two channels instead of a single channel (e.g., as with a simple serial link), but provides good immunity against noise. Differential pair transmission is used for applications such as data processing for connecting peripherals between themselves or to a central processing unit. For example, there has recently been defined a transmission pro
Bongini Stephen
Fleit Kain Gibbons Gutman & Bongini P.L.
Jorgenson Lisa K.
Le Don Phu
STMicroelectronics S.A.
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